Prosecution Insights
Last updated: October 25, 2026
Application No. 18/634,627

Asymmetric MOSFET Devices with Optimized Spacer Thickness

Final Rejection §102§103
Filed
Apr 12, 2024
Examiner
ANYA, IGWE U
Art Unit
Tech Center
Assignee
pSemi Corporation
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
820 granted / 964 resolved
+25.1% vs TC avg
Minimal -4% lift
Without
With
+-3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
29 currently pending
Career history
998
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 29 – 35 and 38 – 45 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fung (US 2008/0179673). PNG media_image1.png 437 648 media_image1.png Greyscale (Claim 29) Fung teaches an asymmetric metal-oxide-semiconductor field-effect transistor (MOSFET) including: (a) a gate structure (260) overlying a body region (20), the gate structure including a conductive layer (126) and having a first side (left) and a second side (right); (b) a first implant region (230) within the body region implanted with a dopant only from the first side (left) of the gate structure and at at least non-90 degrees twist angle, the first implant region located near the first side of the gate structure and not extending to any significant extent into the body region beneath the conductive layer (fig. 3); and (c) a second implant region (232) within the body region implanted with the dopant only from the first side (left) of the gate structure, the second implant region (232) located near the second side (right) of the gate structure and not extending to any significant extent into the body region beneath the conductive layer. The method steps have not been given any patentable weight. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). MPEP 2113. (Claim 30) Fung teaches wherein the first implant region (230) and second implant region (232) include at least one of a halo region or lightly-doped drain region (paragraph (24). (Claim 31) Fung teaches the asymmetric MOSFET, further including a first spacer (244) formed on the first side (left) of the gate structure and a second spacer (244) formed on the second side (right) of the gate structure (260), wherein the first and second spacers have a thickness selected to respectively prevent the first and second implant regions from extending to any significant extent into the body region beneath the conductive layer (fig. 3). (Claim 33) Fung teaches wherein a first non-90 degrees twist angle is in a first quadrant (top left) with respect to the gate structure, and a second non- 90 degrees twist angles (fig. 4 #38) is in a second quadrant (top right) with respect to the gate structure. (Claim 34) Fung teaches wherein a first non-90 degrees twist angle is in a first range of about 0 degree to about 89 degrees (fig. 3 #alpha, paragraph 25) and a second twist angle is in a second range of from about 91 degrees to about 180 degrees (fig. 4 #alpha, paragraph 28) (Claim 35) Fung teaches wherein the dopant is also implanted at a 90 degree twist angle (fig. 3 #34). 38. (Original) An asymmetric metal-oxide-semiconductor field-effect transistor (MOSFET) including: (a) a source region (248); (b) a drain region (250); (c) a body region (20) between the source region and the drain region; (d) a gate structure overlying the body region, the gate structure including a conductive layer (26) and having a source region side (left) and a drain region side (right); (e) a first implant region (230) implanted with a dopant only from the source region side of the gate structure and at at least non-90 degrees twist angle, the first implant region located near the source region side of the gate structure and not extending to any significant extent into the body region beneath the conductive layer (fig. 3); and (f) a second implant region (232) implanted with the dopant only from the source region side of the gate structure, the second implant region located near the drain region side of the gate structure and not extending to any significant extent into the body region beneath the conductive layer. The method steps have not been given any patentable weight. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). MPEP 2113. (Claim 39) Fung teaches wherein the first implant region and second implant region include at least one of a halo region (54) or lightly-doped drain region (230, 232). (Claim 40) Fung teaches the asymmetric MOSFET, further including a first spacer (244 left) formed on the first side (left) of the gate structure and a second spacer (244) formed on the second side right) of the gate structure, wherein the first and second spacers have a thickness selected to respectively prevent the first and second implant regions from extending to any significant extent into the body region beneath the conductive layer, and wherein the extent of implantation (230) into the body beneath the conductive layer is different for the source region compared to the drain region because of the at least one of a halo region or lightly-doped drain region. (Claim 41) Fung teaches the asymmetric MOSFET, further including a first spacer (244) formed on the first side (left) of the gate structure and a second spacer (244) formed on the second side of the gate structure, wherein the first and second spacers have a thickness selected to respectively prevent the first (230) and second implant regions (232) from extending to any significant extent into the body region beneath the conductive layer. (Claim 43) Fung teaches wherein a first non-90 degrees twist angle is in a first quadrant (fig. 3) with respect to the gate structure, and a second non-90 degrees twist angles is in a second quadrant (fig. 4) with respect to the gate structure. (Claim 44) Fung teaches wherein a first non-90 degrees twist angle is in a first range of about 0 degree to about 89 degrees (fig. 3, #28, paragraph 25) and a second twist angle is in a second range of from about 91 degrees to about 180 degrees (fig. 4 #38). (Claim 45) Fung teaches wherein the dopant is also implanted at a 90 degrees twist angle (fig. 3 #34). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 36, 37, 46 and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Fung (US 2008/0179673) in view of Chang et al. (US 2003/0080352). PNG media_image2.png 538 620 media_image2.png Greyscale (Claim 36) Fung lacks wherein the gate structure includes a central gate tab. However, Chang et al. teach wherein the gate structure (fig. 2 #60) includes a serpentine shape for the benefit of increasing the channel width and enhancing the device performance (paragraph 13). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reference for the benefit of increasing the channel width and enhancing the device performance. (Claim 37) Fung lacks wherein the gate structure includes two edge gate tabs, each located near a respective end of the gate structure. However, Chang et al. teach wherein the gate structure (fig. 2 #60) includes a serpentine shape for the benefit of increasing the channel width and enhancing the device performance (paragraph 13). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reference for the benefit of increasing the channel width and enhancing the device performance. (Claim 46) Fung lacks wherein the gate structure includes a central gate tab. However, Chang et al. teach wherein the gate structure (fig. 2 #60) includes a serpentine shape for the benefit of increasing the channel width and enhancing the device performance (paragraph 13). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reference for the benefit of increasing the channel width and enhancing the device performance. (Claim 47) Fung lacks wherein the gate structure includes two edge gate tabs, each located near a respective end of the gate structure. However, Chang et al. teach wherein the gate structure (fig. 2 #60) includes a serpentine shape for the benefit of increasing the channel width and enhancing the device performance (paragraph 13). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reference for the benefit of increasing the channel width and enhancing the device performance. Response to Arguments Applicant's arguments filed July 30, 2026 have been fully considered but they are not persuasive. Applicant argues: Contrary to the characterization of Fung set forth in the Office Action, Fung teaches a conventional FET structure in which dopant is implanted on both sides of a gate structure at a specific tilt angle (not twist angle), as shown in FIGS. 3 and 4 of Fung, in which arrows 28 (FIG. 3) and 38 (FIG. 4) symbolize implants at tilt angle a. See, for example: " Para. 0024: "A first tilt implantation is then preformed to form source extension regions 30 and 230, as illustrated in FIG. 3. The tilt implantation is hence referred to as a source/drain extension (SDE) implantation. The tilt SDE implantation is symbolized by arrows 28." [emphasis added]. " Para. 0028: "Tilt SDE implantation 38 is then performed. Preferably, tilt SDE implantation 38 is performed at a substantially same tilt angle a and using a substantially same dosage as tilt SDE implantation 28 (refer to FIG. 3). In other embodiments, the tilt angles and dosages of tilt SDE implantations 28 and 38 may be different." [emphasis added]. Reply: The method of forming a device is not germane to the device. Under MPEP §2113(i), a product‑by‑process claim is examined for patentability based on the product itself—not the process steps—and is unpatentable if the resulting product is the same as or obvious from prior‑art products, regardless of how those products were made. Applicant argues: Nowhere does Fung even mention dopant implantation at a twist angle, and thus Fung fails to even address, let alone appreciate, the performance problems of a FET arise because the corners formed by the sides and source-side edge of the gate structure have reduced concentrations of dopant. Amended independent claims 29 and 38 now recite "a first implant region within the body region implanted with a first dopant only from the first side of the gate structure and at at least one non- 900 twist angle...". Implanting dopant at a twist angle as recited results in a FET structure that has dopant implanted in locations that tilted implantation alone cannot reach (e.g., the gate structure corners) - a teaching clearly lacking in Fung (which also fails to teach implanting dopant from only one side of a gate structure). Reply: Applicant is not claiming the novel structure. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 October 3, 2026
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Prosecution Timeline

Apr 12, 2024
Application Filed
May 22, 2026
Non-Final Rejection mailed — §102, §103
Jul 30, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.8%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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