Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filed on 07/09/2026. Currently, claims 1-11 and 19-26 are pending in the application. Claims 9-10 and 12-18 are withdrawn and claims 12-18 have been cancelled from Consideration.
Election/Restrictions
Applicant's election without traverse of Group I and Species IA (Figures 1-7), claims 1-8, 11 and 19-26, in the reply filed on 07/09/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Objections
Claim 21 is objected to because of the following informalities: Where it recites “four power transistor” in line 3-4 should be “four power transistors”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11 and 19-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HANADA (US 20210134706 A1).
Regarding claim 1, Figures 1-19 and 31/33/39 of HANADA disclose a semiconductor package, comprising:
a chip level (top surface of 10) having a first side and a second side (bottom side of 10) opposite to the first side, the chip level comprising a plurality of power transistors (Q1-Q6, [0183]) and each power transistor having a source (SS, [0129]) and a gate (G) at the first side;
a first conductive level (pad on Q with wiring, Figure 4) on the first side and including:
a gate connection portion (wiring for G on Q, Figures 3-4) electrically coupled to the gate and a source connection portion (wiring for SS on Q, Figures 3-4) electrically coupled to the source; and a second conductive level (vertical leads coming out from wiring level, Figures 17-19, [0148]) including:
a gate lead-out portion (conductor for G connected to the G pad, Figure 18) electrically coupled to the gate connection portion and a source lead-out portion (SS, Figure 19) electrically coupled with the source connection portion, the first conductive level (pad level, Figures 3-4) being between the second conductive level (vertical leads out wiring level, Figures 17-19) and the chip level.
Regarding claim 2, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, further comprising: a heat sink level (10+3b, Figure 16, [0168]) comprising a plurality of heat sinks (3b with each transistors, [0164]), each heat sink contacting a corresponding power transistor (Q1-Q6) of the plurality of power transistors and the chip level (top surface of 10) being positioned between the heat sink level ( of 10+13b) and the first conductive level (pad and wiring level on top of Q1-Q6).
Regarding claim 3, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, wherein each of the power transistors comprises: a power transistor body at least having a gate region (of G, Figure 34) and a source region (S, Figure 34); an insulating layer (12, Figure 11, [0148]) on the power transistor body; a plurality of through holes (for G and SS, Figure 11) being over the gate region and the source region; and a conductive piece which fills the plurality of through holes, the gate region electrically coupled to the gate connection portion of the first conductive level and the source region is electrically coupled to the source connection portion of the first conductive level.
Regarding claim 4, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, wherein the gate connection portion comprises: a connection body at a geometric center (please see Figure 4/11) of the plurality of power transistors and the gate lead-out portion being on the connection body; and a plurality of connection branches, each of the plurality of connection branches having one end coupled to the connection body and the other end coupled to gate of a corresponding power transistor of the plurality of power transistors (Figures 4/11).
Regarding claim 5, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 4, wherein the plurality of connection branches (wiring in Figure 4) have conductive paths from gates of the plurality of power transistors to the connection body that are consistent (Figure 11).
Regarding claim 6, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 3, wherein the source region has an area (SS in Figure 15) greater than that of the gate region (G), and the source connection portion has an area greater than or equal to that of the source region (Figure 15).
Regarding claim 7, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, wherein a number of the plurality of power transistors is four (considering the device in claim 1 with four transistors as shown in Figure 32).
Regarding claim 8, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, wherein the first conductive level and the second conductive level are made of a material selected from at least one of: copper; silver; aluminum; and soldering tin (claims 31-32 of HANADA).
Regarding claim 11, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 1, further comprising: a power transistor (Q1-Q6) connector at a corresponding position of each power transistor of the plurality of power transistors, the power transistor connector comprising a plurality of through holes filled with a conductive piece (Figure 31), such that a gate of a power transistor is electrically coupled to a corresponding gate connection portion of the first conductive level and a source of a power transistor is electrically coupled to a corresponding source connection portion of the first conductive level ([0204]).
Regarding claim 19, Figures 1-19 and 31/33/39 of HANADA disclose a power module, comprising:
a substrate (10, [1060]) having a gate wiring board (Figure 4/15, conductor in the middle of transistors Q connected to G) and a source wiring board (Figure 4/15, conductor in the middle of transistors Q connected to SS);
a semiconductor package (4a) being positioned on the substrate, the package including:
a chip level (top surface of 10) having a first side and a second side opposite to the first side, the chip level comprising a plurality of power transistors (Q1-Q6, [0182]) having a gate (G) and a source (SS, [0145]);
a first conductive level (pad level on the Q1-Q6) on the first side and including:
a gate connection portion (wiring lines connecting the gate pads G on the transistors Q1-Q6) electrically coupled to the gate and a source connection portion (wiring lines connecting the source pads SS on the transistors Q1-Q6) electrically coupled to the source; and
a second conductive level (verticals connecting conductors, Figure 11) including: a gate lead-out portion (vertical conductor of G) electrically coupled to the gate connection portion and a source lead-out portion (vertical conductor of SS) electrically coupled with the source connection portion, the first conductive level being between the second conductive level and the chip level, and the gate lead-out portion being electrically coupled to the gate wiring board via a gate line and the source lead-out portion being electrically coupled to the source wiring board via a source line (Figures 18-19).
Regarding claim 20, Figures 1-19 and 31/33/39 of HANADA disclose that the power module of claim 19, wherein the gate wiring board and the source wiring board are coupled to a drive module respectively via a corresponding part of a lead frame (Figure 2/31 taches part of a lead frame connecting G and SS).
Regarding claim 21, Figures 1-19 and 31/33/39 of HANADA disclose a semiconductor package, comprising:
a chip level (top surface of 10) having a first side and a second side opposite to the first side, the chip level including four power transistors (Q1-Q4, [0182]) and each respective power transistor of the at least four power transistors having a source (SS, [0148]) and a gate (G) at the first side;
a first conductive level (pad level on the transistors Q1-Q2) on the first side, the first conductive level including:
a gate connection portion (wiring connecting G, Figures 3-4) electrically coupled to the gate of each respective power transistor of the at least four power transistors and a source connection portion (wiring connecting SS, Figures 3-4) electrically coupled to the source of each of the four power transistors; and
a second conductive level (vertical conductor on the transistors, Figure 31) on the first conductive level, the second conductive level including:
a gate lead-out portion (vertical conductor for G, Figure 31) electrically coupled to the gate connection portion and a source lead-out portion (vertical conductor for SS, Figure 31) electrically coupled to the source connection portion, the first conductive level being between the second conductive level and the chip level (top surface of 10), wherein the gate connection portion includes a connection body at a geometric center of the at least four power transistors and a plurality of connection branches, each respective connection branch of the plurality of connection branches having one end coupled to the connection body and an opposing end coupled to a respective gate of a corresponding power transistor of the at least four power transistors (Figure 31/39).
Regarding claim 22, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 21, wherein the gate lead-out portion (G, Figures 31/39) is on the connection body.
Regarding claim 23, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 21, wherein the plurality of connection branches (Figures 31/39) have conductive paths from gates of the four power transistors to the connection body that are consistent.
Regarding claim 24, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 21, further comprising: a heat sink level (10+3b, [0164] and [0168]) comprising a plurality of heat sinks (3b, [0164], soldering layer acts as heat sink, Figure 16), each heat sink contacting a corresponding power transistor of the four power transistors (Q1-Q4) and the chip level being positioned between the heat sink level and the first conductive level.
Regarding claim 25, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 21, wherein each of the four power transistors comprises: a power transistor body at least having a gate region (G) and a source region (SS); an insulating layer (12, [0168]) on the power transistor body; a plurality of through holes (holes in 12, Figure 11) being over the gate region and the source region; and a conductive piece which fills the plurality of through holes, the gate region electrically coupled to the gate connection portion of the first conductive level and the source region electrically coupled to the source connection portion of the first conductive level.
Regarding claim 26, Figures 1-19 and 31/33/39 of HANADA disclose that the semiconductor package of claim 25, wherein the source region (SS, Figure 15/34) has an area greater than that of the gate region (G), and the source connection portion has an area greater than or equal to that of the source region.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813
Prosecution Insights