DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/13/2024 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the upper surface of must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5-12, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0102352 A1, hereafter Lee), and further in view of Jang (US 2017/0125532 A1).
Regarding claim 1, Fig. 9B of Lee teaches a semiconductor device comprising:
a substrate (100, [0057]);
a bit line (BL, [0059]) extending in a first horizontal direction on the substrate (100);
a channel layer (CP, [0069]) disposed on the bit line (BL) and including:
a first portion (see annotated Fig. 9B) extending in the first horizontal direction, and
a second portion (see annotated Fig. 9B) connected to the first portion, including a first sidewall (see annotated Fig. 9B) and a second sidewall (see annotated Fig. 9B) opposite to the first sidewall, and extending in a vertical direction perpendicular to an upper surface of the substrate (100);
a gate insulating layer (Gox, [0069]) formed to conformally cover the first portion on an upper surface of the first portion of the channel layer (CP) and the second portion on the first sidewall of the second portion of the channel layer (CP); and
a word line (WL1/WL2, [0069]) disposed on a sidewall of the [gate insulating layer (Gox)] and extending in a second horizontal direction perpendicular to the first horizontal direction,
wherein the channel layer (CP) includes an oxide semiconductor material ([0080]).
Lee fails to disclose a work function adjustment layer conformally formed on the gate insulating layer.
However, Jang in Fig. 3 teaches a device similar to Lee in which a dipole induction layer (110, [0029]) is formed to conform to the gate dielectric (107, [0029]). This dipole induction layer adjusts the work function of the device [0021]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to include the dipole induction layer of Jang in order to adjust the threshold voltage of the device as Jang teaches in [0021].
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Regarding claim 2, Lee in view of Jang teach the semiconductor device of claim 1. Jang further teaches the work function adjustment layer (dipole induction layer, 110, [0029]) includes a material having a work function of about 4.9 eV or more (Jang teaches the dipole induction layer to be titanium dioxide [0005] which is known to have a work function of at least 4.9 eV, as evidenced by Andriy Borodin and Michael Reichling [Abstract, NPL)).
Regarding claim 3, Lee in view of Jang teach the semiconductor device of claim 1. Jang further teaches the work function adjustment layer (dipole induction layer, 110, [0029]) includes at least one of indium oxide (In.sub.2O.sub.3), titanium dioxide (TiO.sub.2) ([0005]), molybdenum trioxide (MoO.sub.3), and tungsten trioxide (WO.sub.3), and Lee teaches the oxide semiconductor material includes InGaZnOx (IGZO) ([0080]).
Regarding claim 5, Lee in view of Jang teach the semiconductor device of claim 1. Fig. 9B of Lee further teaches wherein:
an upper surface of the first portion (see annotated Fig. 9B) of the channel layer (CP, [0069]) is coplanar (here they meet at an interface, making them coplanar) with a lower surface of a horizontal portion of the gate insulating layer (Gox, [0069]).
Lee in view of Jang teach a lower surface of the word line (WL1/WL2 of Lee, [0069]) is coplanar with a lower surface of the work function adjustment layer (dipole induction layer of Jang, 110, [0029]). As the work function adjustment layer is formed in a shape similar to the gate insulating layer and the channel layer, the upper surface of the horizontal potion (similar to the upper layer of the first portion) is a lower surface under BRI, and as they surfaces meet at an interface, they are coplanar.
While Lee in view of Jang do not explicitly teach an upper surface of the word line is coplanar with an upper surface of the work function adjustment layer, Jang shows in Fig. 3 the gate G (analogous to the word line of Lee) is coplanar with the dipole induction layer 110. One of ordinary skill in the art would know to form the work function adjustment layer in the modified device of Lee in view of Jang to be coplanar with the word line.
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Regarding claim 6, Lee in view of Jang teach the semiconductor device of claim 1. Lee further teaches wherein the uppermost surface of the second portion (see annotated Fig. 9B) of the channel layer (CP, [0069]) and the uppermost surface of a vertical portion of the gate insulating layer (Gox, [0069]) are disposed at the same vertical level.
Regarding claim 7, Lee in view of Jang teach the semiconductor device of claim 1. While Lee in view of Jang do not explicitly teach a vertical portion of the work function adjustment layer has an upper surface disposed at the same vertical level as a level of an upper surface of the word line, Jang shows in Fig. 3 the gate G (analogous to the word line of Lee) is coplanar with the dipole induction layer 110. One of ordinary skill in the art would know to form the work function adjustment layer in the modified device of Lee in view of Jang has an upper surface disposed at the same vertical level as a level of an upper surface of the word line.
Regarding claim 8, Lee in view of Jang teach the semiconductor device of claim 1. Lee further teaches in Fig. 9B wherein the gate insulating layer (Gox, [0069]) has an upper surface disposed at a level higher than an upper surface of the word line (WL1/WL2, [0069]).
Regarding claim 9, Lee in view of Jang teach the semiconductor device of claim 1. Fig. 9B of Lee further teaches:
a mold insulating layer (first insulating pattern, 115, [0072]) disposed on the bit line (BL, [0059]) and covering the second sidewall (see annotated Fig. 9B) of the channel layer (CP, [0069).
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Regarding claim 10, Lee in view of Jang teach the semiconductor device of claim 1. Fig. 9B of Lee further teaches:
a conductive contact pattern (landing pad, LP, [0094-0095]) connected to the second portion (see annotated Fig. 9B) of the channel layer (CP, [0069]); and
a capacitor structure (DSP, [0098]) connected to the conductive contact pattern (LP).
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Regarding claim 11, Fig. 9B of Lee teaches a semiconductor device comprising:
a substrate (100, [0057]);
a bit line (BL, [0059]) extending in a first horizontal direction on the substrate (100);
a mold insulating layer (first insulating pattern, 115, [0072]) covering the bit line (BL) on the substrate (100) and including a mold opening;
a first cell transistor (see annotated Fig. 9B) disposed on a first sidewall (see annotated Fig. 9B) of the mold opening; and
a second cell transistor (see annotated Fig. 9B) disposed on a second sidewall (see annotated Fig. 9B) of the mold opening,
wherein each of the first cell transistor and the second cell transistor includes:
a channel layer (CP, [0069]) disposed on the bit line (BL) and including:
a first portion (see annotated Fig. 9B) extending in the first horizontal direction, and
a second portion (see annotated Fig. 9B) connected to the first portion and extending in a vertical direction perpendicular to an upper surface of the substrate (100);
a gate insulating layer (Gox, [0069]);
a word line (WL1/WL2, [0069]) extending in a second horizontal direction perpendicular to the first horizontal direction; and
a contact (landing pad, LP, [0094-0095]) disposed on the second portion of the channel layer (CP),
wherein the channel layer (CP) includes an oxide semiconductor material ([0080]).
Lee fails to teach a work function adjustment layer disposed on the first portion and the second portion of the channel layer, the gate insulating layer located between the channel layer and the work function adjustment layer, or a word line disposed on a sidewall of the work function adjustment layer.
However, Jang in Fig. 3 teaches a device similar to Lee in which a dipole induction layer (110, [0029]) is formed to conform to the gate dielectric (107, [0029]). This dipole induction layer adjusts the work function of the device [0021]. The placement of the dipole induction layer would allow for the gate insulating layer located between the channel layer and the work function adjustment layer, and the word line disposed on a sidewall of the work function adjustment layer. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to include the dipole induction layer of Jang in order to adjust the threshold voltage of the device as Jang teaches in [0021].
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Regarding claim 12, Lee in view of Jang teach the semiconductor device of claim 11. Lee further teaches in Fig. 9B, wherein the channel layer (CP, [0069]) of the first cell transistor (see annotated Fig. 9B) and the channel layer of the second cell transistor (see annotated Fig. 9B) have a mirror symmetrical shape with respect to each other (CP in particular is described as mirror symmetrical in [0161]).
Regarding claim 14, Lee in view of Jang teach the semiconductor device of claim 11. Jang further teaches the work function adjustment layer (dipole induction layer, 110, [0029]) includes a material having a work function of about 4.9 eV or more (Jang teaches the dipole induction layer to be titanium dioxide [0005] which is known to have a work function of at least 4.9 eV, as evidenced by Andriy Borodin and Michael Reichling [Abstract, NPL)).
Regarding claim 15, Lee in view of Jang teach the semiconductor device of claim 11. Jang further teaches the work function adjustment layer (dipole induction layer, 110, [0029]) includes at least one of indium oxide (In.sub.2O.sub.3), titanium dioxide (TiO.sub.2) ([0005]), molybdenum trioxide (MoO.sub.3), and tungsten trioxide (WO.sub.3), and Lee teaches the oxide semiconductor material includes InGaZnOx (IGZO) ([0080]).
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Regarding claim 16, Lee in view of Jang teach the semiconductor device of claim 11. Fig. 9B of Lee further teaches wherein:
an upper surface of the first portion (see annotated Fig. 9B) of the channel layer (CP, [0069]) is coplanar (here they meet at an interface, making them coplanar) with a lower surface of a horizontal portion of the gate insulating layer (Gox, [0069]).
Lee in view of Jang teach a lower surface of the word line (WL1/WL2 of Lee, [0069]) is coplanar with a lower surface of the work function adjustment layer (dipole induction layer of Jang, 110, [0029]). As the work function adjustment layer is formed in a shape similar to the gate insulating layer and the channel layer, the upper surface of the horizontal potion (similar to the upper layer of the first portion) is a lower surface under BRI, and as they surfaces meet at an interface, they are coplanar.
While Lee in view of Jang do not explicitly teach an upper surface of the word line is coplanar with an upper surface of the work function adjustment layer, Jang shows in Fig. 3 the gate G (analogous to the word line of Lee) is coplanar with the dipole induction layer 110. One of ordinary skill in the art would know to form the work function adjustment layer in the modified device of Lee in view of Jang to be coplanar with the word line.
Claim(s) 4, 13, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Jang, and further in view of Kamata et al. (US 2015/0262691 A1, hereafter Kamata).
Regarding claim 4, Lee in view of Jang teach the semiconductor device of claim 1. Lee in view of Jang are silent on the work function adjustment layer is formed to have a thickness of about 1 nm to 20 nm. One of ordinary skill in the art would know to use a thickness for a work function adjustment layer known in the art before the effective filing date of the present application. Kamata teaches a similar memory device in which the work function adjusting material is formed to be 3-10 nm thick, fully within the range of the present application [0310].
Regarding claim 11, Lee in view of Jang teach the semiconductor device of claim 11. Lee in view of Jang are silent on the work function adjustment layer is formed to have a thickness of about 1 nm to 20 nm. One of ordinary skill in the art would know to use a thickness for a work function adjustment layer known in the art before the effective filing date of the present application. Kamata teaches a similar memory device in which the work function adjusting material is formed to be 3-10 nm thick, fully within the range of the present application [0310].
Regarding claim 17, Fig. 9B of Lee teaches a semiconductor device comprising:
a substrate (100, [0057]);
a peripheral circuit region (SA in Fig. 4B) on the substrate (100);
a plurality of peripheral circuits (decoders 2 and 4, [0067]) disposed in the peripheral circuit region (SA);
a plurality of lower conductive lines (BL, [0059]) disposed in parallel to each other and respectively connected to the plurality of peripheral circuits (2 and 4, described as electrically connected in [0067]);
a mold insulation pattern (first insulating pattern, 115, [0072]) disposed on the plurality of lower conductive lines (BL) and defining a transistor region extending long in a first horizontal direction;
a plurality of channel structures (CP, [0069]) arranged in a row in the first horizontal direction in the transistor region and each including a vertical channel portion (see “second portion” in annotated Fig. 9B) facing a sidewall of the mold insulation pattern (115);
a gate insulating layer (Gox, [0069]) located between the plurality of channel structures and the work function adjustment layer;
an upper conductive line (WL1/WL2, [0069]) disposed on the plurality of channel structures (CP) in the transistor region, having a sidewall facing the vertical channel portions of each of the plurality of channel structures (CP), and extending long in a second horizontal direction perpendicular to the first horizontal direction; and
a plurality of conductive contact patterns (landing pad, LP, [0094-0095]) connected to the vertical channel portions of the plurality of channel structures (CP), respectively,
wherein the plurality of channel structures (CP) each includes an oxide semiconductor material ([0080]).
Lee fails to teach a work function adjustment layer in the transistor region and covering the plurality of channel structures the gate insulating layer located between the plurality of channel structures and the work function adjustment layer, and the work function adjustment layer includes a material having a work function of about 4.9 eV or more.
However, Jang in Fig. 3 teaches a device similar to Lee in which a dipole induction layer (110, [0029]) is formed to conform to the gate dielectric (107, [0029]). This dipole induction layer adjusts the work function of the device [0021]. The placement of the dipole induction layer would allow for the gate insulating layer located between the plurality of channel structures and the work function adjustment layer, and the word line disposed on a sidewall of the work function adjustment layer. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to include the dipole induction layer of Jang in order to adjust the threshold voltage of the device as Jang teaches in [0021]. Jang further teaches the dipole induction layer to be titanium dioxide [0005] which is known to have a work function of at least 4.9 eV, as evidenced by Andriy Borodin and Michael Reichling [Abstract, NPL).
Lee in view of Jang are silent on having a thickness of about 1 nm to about 20 nm. One of ordinary skill in the art would know to use a thickness for a work function adjustment layer known in the art before the effective filing date of the present application. Kamata teaches a similar memory device in which the work function adjusting material is formed to be 3-10 nm thick, fully within the range of the present application [0310].
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Regarding claim 18, Lee in view of Jang, and in view of Kamata teach the semiconductor device of claim 17. Lee further teaches:
the transistor region includes a plurality of transistors (see “first cell transistor” and “second cell transistor” in annotated Fig. 9B) including the plurality of channel structures (see annotated Fig. 9B),
the plurality of transistors include two transistors facing each other in the first horizontal direction (see annotated Fig. 9B), and
the two transistors share one channel structure (CP, [0069]) selected from the plurality of channel structures.
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Regarding claim 19, Lee in view of Jang in view of Kamata teach the semiconductor device of claim 17. Lee further teaches:
the uppermost surface of the upper conductive line (WL1/WL2, [0069]) is closer to the substrate (100, [0057]) than the uppermost surface of the gate insulating layer (Gox, [0069]), and
an upper surface of a horizontal portion of one channel structure (CP, [0069]) is coplanar (here they meet at an interface, making them coplanar) with a lower surface of a horizontal portion of the gate insulating layer (Gox, [0069]).
Regarding claim 20, Lee in view of Jang in view of Kamata teach the semiconductor device of claim 17. Jang further teaches the work function adjustment layer (dipole induction layer, 110, [0029]) includes at least one of indium oxide (In.sub.2O.sub.3), titanium dioxide (TiO.sub.2) ([0005]), molybdenum trioxide (MoO.sub.3), and tungsten trioxide (WO.sub.3), and Lee teaches the oxide semiconductor material includes InGaZnOx (IGZO) ([0080]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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