DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 1), (claims 1-6, 8, 10-15, 17) in the reply filed on 07/09/2026 is acknowledged. However claims 10-15, 17 do not read on elected species of Fig. 1 and therefore withdrawn from consideration.
Claims 7, 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/09/26.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “roughness” in claim 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 recites “a roughness” is indefinite as it is not shown or defined how rough it is and therefore any natural roughness during formation of any layers with known semiconductor process is considered for examination purpose.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al (US 2019/0103227 A1).
Regarding claim 1: Lu teaches in Fig. 1-2 about a capacitor, comprising:
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a first electrode 105;
a second electrode 102; and
a first capacitor dielectric layer (103 + 104) disposed between the first electrode and the second electrode, wherein the first capacitor dielectric layer comprises a first dielectric layer 104 and a second dielectric layer 103, the first dielectric layer 104 comprises an inorganic dielectric layer [0024], and the second dielectric layer comprises an organic dielectric layer [0035], wherein the first dielectric layer is located between the first electrode and the second dielectric layer (as shown), and the second dielectric layer is located between the first dielectric layer 104 and the second electrode 102.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6, 8 are rejected under 35 U.S.C. 103 as being obvious over Lu et al (US 2019/0103227 A1) in view of Kuwajima et al. (TW 200807465 A)
Regarding claim 2: Lu does not explicitly talk about wherein the first dielectric layer has a first surface, the first surface is in contact with the second dielectric layer, the second dielectric layer has a second surface, the second surface is in contact with the second electrode, and a roughness of the first surface is greater than a roughness of the second surface.
However it is known in the art, during manufacturing there is always some roughness between layers as ideally it’s not possible to form any smooth surface and Lee teaches in [0035] that the 2nd surface (as marked the interface between 102 and 103) roughness is controlled and reduced which would therefore be less than the natural surface roughness of the 1st surface (as marked between 103 and 104) depending on layers forming process like CVD, PVD, or CMP etc. Furthermore Kuwajima teaches in page 2 and Fig. 14 n the dielectric layer 103, a portion having a particularly small thickness sometimes occurs, and the insulation of the portion is lowered, resulting in a decrease in the private pressure resistance of the capacitor. In this case, it is easy to cause a short circuit failure of the capacitor due to dielectric breakdown of the dielectric layer 1 (10). Further, when the thickness of the dielectric layer 103 is not uniform, the variation in withstand voltage of the capacitor between the products becomes large. Kuwajima also teaches that a planarization film is used to improve the thickness uniformity of the dielectric film.
Therefore it would have been obvious to a person of ordinary skill in the art at the time of the application was filed to realize from Lee's and Kuwajima’s teachings to have the feature as claimed and thereby to improve capacitance performance and current leakage issues (Lee, [0036]) and avoid short circuit failure for the capacitor (Kuwajima, Page).
Regarding claim 3: Lu does not explicitly talk about wherein a distribution area of the first electrode, the second electrode, and the first capacitor dielectric layer is less than or equal to 50 microns x 50 microns.
However Lee teaches in Fig. 2 and [0030] and well known in the art, higher capacitance is associated with larger area and depending on application delay is designed/optimized which also depends on area of the capacitor.
Thus, it would have been obvious to one of the ordinary skill in the art at the time the application was filed to use have the feature of area size with routine experiment and optimization since the area is critical for delay for signal transmission. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 4: Lee teaches in Fig. 1 about a substrate 101, wherein the first electrode is disposed on the substrate, and the first capacitor dielectric layer and the second electrode are stacked on the first electrode.
Regarding claim 5: Lee teaches in Fig. 3B wherein the substrate has a groove 101a , and the first electrode, the first capacitor dielectric layer, and the second electrode cover the groove.
Regarding claim 6: Lee teaches in [0021] wherein the substrate comprises: a first material layer 101; and a second material layer (oxide layer) disposed on the first material layer.
Regarding claim 8: Lee teaches in [0021] and Fig. 1 wherein the substrate has a groove, the groove is distributed in the second material layer, and the first electrode, the first capacitor dielectric layer, and the second electrode cover the groove.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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