DETAILED ACTION
This action is responsive to the communication filed 2 September 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Election/Restrictions
Applicant’s election without traverse of Species 19 (FIG. 10B) embodiment in the reply filed on 2 September 2026 is acknowledged.
Regarding Applicant’s listing of claims 18, 20-23, 25-31, 34, and 38-42 as readable on the elected species, however, the Examiner respectfully notes that claim 26 does not belong to the elected Species 19 (FIG. 10B) embodiment. Claim 26 recites the limitation “the first 3D capacitor vertically extending from below a top of the conductive via to below a bottom of the conductive via . . . .” Applicant’s elected Species 19 embodiment is depicted in FIG. 10B, however, which shows wherein the 3D capacitor extends below the top of the conducive via but not below a bottom of the conductive via. The other unelected embodiments is depicted in, e.g., FIG. 11B, shows the first 3D capacitor vertically extending from below a top of the conductive via to below a bottom of the conductive via.
Accordingly, claim 26 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 18, 20-22, 27, 28, and 38 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2022/0077216 (filed May 10, 2021) (hereinafter “Lim”).
Regarding independent claim 18, Lim discloses: A method of forming an image sensor integrated chip (IC), comprising: providing a first substrate having a plurality of pixel regions within a pixel array (FIGS. 3/12/13, depicting a substrate 101 having a plurality of unit pixels UP within an active pixel sensor array 10, [0036], [0086]);
forming one or more ILD layers on the first substrate (FIGS. 3/12/13, depicting a wiring structure 200 including one or more interlayer insulation films 210/220/230/240/250/260, [0094], [0135]);
forming an opening extending vertically through the one or more ILD layers (FIGS. 12/13, depicting capacitor trenches CT extending vertically through, e.g., the interlayer insulation film 230, [0108]),
wherein the opening is laterally set-back from opposing sides of one of the plurality of pixel regions by non-zero distances (FIGS. 12/13, depicting wherein the capacitor trenches CT are laterally set back from opposing sides of the unit pixels UP by a non-zero distance);
forming a capacitor stack within the opening and over the one or more ILD layers (FIGS. 12/13, depicting wherein a plurality of layers forming the capacitors C1/C2, including lower electrode 410, capacitor dielectric film 420, and upper electrode 430, are formed within the capacitor trenches CT and over, e.g., the interlayer insulation film 230, [0107]); and
patterning the capacitor stack to form a capacitor having a horizontally extending segment over the one or more ILD layers and a vertically extending segment extending through the one or more ILD layers (FIGS. 12/13, depicting wherein capacitors C1/C2 are formed having horizontally extending segments over, e.g., the interlayer insulation film 230 and vertically extending segments through, e.g., the interlayer insulation film 230, [0109]).
Regarding claim 20, Lim further discloses forming a plurality of image sensing elements within the plurality of pixel regions (FIGS. 12/13, depicting wherein photoelectric conversion elements PD are formed within the unit pixels UP, [0051]).
Regarding independent claim 21, Lim discloses: A method of forming an integrated chip, comprising: forming a plurality of image sensing elements within a plurality of pixel regions of a substrate (FIGS. 3/12/13, depicting wherein photoelectric conversion elements PD are formed within the unit pixels UP of a substrate 101 within an active pixel sensor array 10, [0051], [0036], [0086]);
forming a plurality of conductive interconnects along a surface of the substrate (FIGS. 12/13, depicting electrode pads 235/245 formed along a surface of the substrate 101); and
forming a plurality of three-dimensional (3D) capacitors onto the plurality of conductive interconnects and within respective ones of the plurality of pixel regions (FIGS. 12/13, depicting capacitors C1/C2 formed onto the plurality of electrode pads 235/245 and within respective ones of the plurality of unit pixels UP, [0107]),
wherein the plurality of 3D capacitors respectively comprise a base region extending in parallel to the surface of the substrate and one or more fingers extending outward from the base region along a direction perpendicular to the surface of the substrate (FIGS. 12/13, depicting wherein the capacitors C1/C2 include a region extending parallel to the surface of the substrate 101 and one or more regions extending outward from the region extending parallel to the surface of the substrate 101 and perpendicular to the surface of the substrate 101).
Regarding claim 22, Lim further discloses wherein respective ones of the plurality of 3D capacitors are entirely confined within one of the plurality of pixel regions (FIGS. 12/13, depicting wherein the capacitors C1/C2 are entirely confined within the unit pixel UP).
Regarding claim 27, Lim further discloses forming one or more upper dielectric layers over the plurality of conductive interconnects and the plurality of 3D capacitors (FIGS. 12/13, depicting wherein interlayer insulation films 250/260 are formed over the electrode pads 235/245); forming a plurality of conductive features within the one or more upper dielectric layers (FIGS. 12/13, depicting wherein a plurality of wirings 252 and 262 are formed within the interlayer insulation films 250/260, [0094]); forming an additional integrated chip structure comprising a plurality of pixel support devices (FIGS. 12/13, depicting wherein transistors TR1-TR3 are formed, which may be pixel support devices, [0081]); and bonding the plurality of conductive features to one or more additional conductive features on the additional integrated chip structure (Lim FIGS. 12/13, depicting wherein the wirings 252 and 262, as part of the wiring structure 200, are bonded to conductive features of the transistors TR1-TR3, such as, e.g., short vias 217, [0095]).
Regarding claim 28, Lim further discloses forming a plurality of isolation structures within the substrate, wherein the plurality of isolation structures laterally separate the plurality of pixel regions from one another (FIGS. 12/13, depicting pixel separation patterns 105 formed in the substrate 101, wherein the pixel separation patterns 105 laterally separate the unit pixels UP from one another, [0088]).
Regarding claim 38, Lim further discloses patterning the capacitor stack to form a plurality of capacitors respectively disposed within one of the plurality of pixel regions (FIGS. 12/13, depicting wherein a plurality of capacitors C1/C2 are formed within one of the plurality of unit pixels UP, [0109]); and forming a plurality of peripheral interconnect structures within the one or more ILD layers (FIGS. 12/13, depicting e.g., vias 247/249 formed within, e.g., the interlayer insulation film 230, [0124]), wherein the plurality of peripheral interconnect structures are respectively disposed within one of the plurality of pixel regions (FIGS. 12/13, depicting wherein the plurality of vias 247/249 are disposed within the unit pixels UP).
Claims 31, 34, and 37 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2020/0111831 (filed May 9, 2019) (hereinafter “Choi”).
Regarding independent claim 31, Choi discloses: A method of forming an integrated chip, comprising: forming an image sensing element within a pixel region within a substrate (FIGS. 10A/11-18, depicting photoelectric conversion region 111 formed within a pixel region PR within a semiconductor substrate 101, [0081]);
depositing an etch stop layer onto a first interlevel dielectric (ILD) layer over the substrate (FIGS. 10A/11-18, depicting formation of interlayer insulation layer 220, on which an etch stop layer is formed, over the semiconductor substrate 101, [0150]-[0151]);
depositing a lower second ILD layer onto the etch stop layer (FIGS. 10A/11-18, depicting mold insulation layer 230 deposited on the etch stop layer and interlayer insulation layer 220);
etching the first ILD layer, the etch stop layer, and the lower second ILD layer to form one or more capacitor openings (FIGS. 10A/11-18, depicting formation of lower electrode holes extending by etching the interlayer insulation layer 220, etch stop layer, and mold insulation layer 230, [0153]);
forming a capacitor stack within the one or more capacitor openings and over the lower second ILD layer (FIGS. 10A/11-18, depicting formation of lower electrodes 231, dielectric pattern 233, and upper electrode 235, [0103]);
patterning the capacitor stack to form a 3D capacitor structure within the pixel region (FIGS. 10A/11-18, depicting wherein the of lower electrodes 231, dielectric pattern 233, and upper electrode 235 are patterned and thereby form a 3D capacitor within the pixel region PR);
depositing an upper second ILD layer onto the lower second ILD layer and the 3D capacitor structure (FIGS. 10A/11-18, depicting wherein interlayer insulation layer 240 is deposited on the mold insulation layer 230 and 3D capacitor); and
forming a peripheral interconnect vertically extending through the lower second ILD layer and the upper second ILD layer and laterally confined within the pixel region (FIGS. 10A/11-18, depicting formation of contact plugs CP3 vertically extending through the interlayer insulation layer 240 and mold insulation layer 230, [0111]),
wherein the peripheral interconnect is laterally separated from the 3D capacitor structure by the lower second ILD layer and the upper second ILD layer (FIGS. 10A/11-18, depicting wherein the contact plugs CP3 are laterally separated from the 3D capacitor by the insulation layer 240 and mold insulation layer 230).
Regarding claim 34, Choi further discloses wherein the pixel region is arranged between neighboring isolation structures within the substrate, the neighboring isolation structures vertically extending through the substrate in a cross-sectional view (FIGS. 10A/11-18, depicting wherein the photoelectric conversion regions 111 are arranged between, e.g., isolation structures 105 within the substrate 101, wherein the isolation structures extend through the substrate 101 in a cross-sectional view, [0140]).
Regarding claim 37, Choi further discloses forming a second image sensing element within a second pixel region within the substrate (FIGS. 3/5/10A/11-18, depicting a plurality of pixel regions PR in the pixel array 10, each including a photoelectric conversion region 111), the second pixel region neighboring the pixel region (FIGS. 3/5/10A/11-18, depicting wherein the plurality of pixel regions PR in the pixel array 10 neighbor each other); and patterning the capacitor stack to form a second 3D capacitor structure within the second pixel region (FIGS. 3/5/10A/11-18, depicting wherein each of the pixel regions PR include 3D capacitors), wherein the peripheral interconnect is laterally between the 3D capacitor structure and the second 3D capacitor structure (FIGS. 3/5/10A/11-18, depicting wherein various interconnection structures, including contact plugs CP3 are formed between the various 3D capacitors).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Choi.
Regarding claim 23, Lim does not specifically disclose depositing an etch stop layer and an interlevel dielectric layer over the surface of the substrate; etching the etch stop layer and the interlevel dielectric layer to form a plurality of capacitor openings; forming a first electrode layer within the plurality of capacitor openings; forming a first capacitor dielectric layer onto the first electrode layer and within the plurality of capacitor openings; forming a second electrode layer onto the first capacitor dielectric layer and within the plurality of capacitor openings; and patterning the first electrode layer, the first capacitor dielectric layer, and the second electrode layer to form the plurality of 3D capacitors.
In the same field of endeavor, Choi discloses a method of forming an image sensor, including steps of forming a 3D capacitor including steps of depositing an etch stop layer and an interlevel dielectric layer over the surface of the substrate (FIGS. 10A/11-18, depicting formation of interlayer insulation layer 220, on which an etch stop layer is formed, over the semiconductor substrate 101, [0150]-[0151]); etching the etch stop layer and the interlevel dielectric layer to form a plurality of capacitor openings (FIGS. 10A/11-18, depicting formation of lower electrode holes extending by etching the interlayer insulation layer 220, etch stop layer, and mold insulation layer 230, [0153]); forming a first electrode layer within the plurality of capacitor openings (FIGS. 10A/11-18, depicting formation of lower electrodes 231, dielectric pattern 233, and upper electrode 235 in the lower electrode holes, [0103]); forming a first capacitor dielectric layer onto the first electrode layer and within the plurality of capacitor openings (FIGS. 10A/11-18, depicting formation of lower electrodes 231, dielectric pattern 233, and upper electrode 235 in the lower electrode holes, [0103]); forming a second electrode layer onto the first capacitor dielectric layer and within the plurality of capacitor openings (FIGS. 10A/11-18, depicting formation of lower electrodes 231, dielectric pattern 233, and upper electrode 235 in the lower electrode holes, [0103]); and patterning the first electrode layer, the first capacitor dielectric layer, and the second electrode layer to form the plurality of 3D capacitors (FIGS. 10A/11-18, depicting wherein the of lower electrodes 231, dielectric pattern 233, and upper electrode 235 are patterned and thereby form a 3D capacitor within the pixel region PR). Regarding the formation of the 3D capacitors, in [0110], Choi states: “According to example embodiments, because the first and second lower electrodes 231 a and 231 b have a relatively high aspect ratio and a cylinder shape, surface areas of the first and second lower electrodes 231 a and 231 b may increase. In addition, because the first and second lower electrodes 231 a and 231 b are arranged in a zigzag pattern, the number of the first and second lower electrodes 231 a and 231 b arranged on the first and second lower pad electrodes 222 a and 222 b may increase. Thus, the capacitance of the first and second capacitors (see C1 and C2 of FIG. 3) may increase. Accordingly, during the global shutter operation, the loss of the charges and the noise generation may be reduced or prevented, such that the shutter efficiency may be improved.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed method of Lim by substituting the method of forming a capacitor of Choi in order to increase surface area of the electrodes, increase the number of electrodes, and increase the capacitance of the capacitor, thereby reducing noise generation and improving shutter efficiency. See Choi [0110].
Regarding claim 25, Lim in view of Choi further discloses wherein a first 3D capacitor of the plurality of 3D capacitors is arranged within a first pixel region of the plurality of pixel regions (Lim FIGS. 3/12/13, depicting wherein a plurality of capacitors C1/C2 are arranged within a unit pixel UP within a plurality of unit pixels UP); and wherein a peripheral interconnect structure is arranged within the first pixel region, the first 3D capacitor being laterally separated from the peripheral interconnect structure by the interlevel dielectric layer (FIGS. 12/13, depicting wherein, e.g., vias 247/249 are formed within, e.g., the interlayer insulation films 230/240, wherein the vias 247/249 and capacitors C1/C2 are laterally separated by the interlayer insulation films 230/240).
Claims 29, 30, and 39-42 are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of U.S. Patent Publication No. 2020/0135844 (published Apr. 30, 2020) (hereinafter “Takahashi”).
Regarding claim 29, Lim does not specifically disclose forming a second plurality of conductive interconnects on a second substrate; and forming a second plurality of 3D capacitors onto the second plurality of conductive interconnects and within respective ones of the plurality of pixel regions, wherein the second plurality of 3D capacitors respectively comprise a second base region and one or more second fingers extending outward from the second base region towards the second substrate.
In the same field of endeavor, Takahashi discloses a method of forming an image sensor, including steps of forming a 3D capacitor including steps of forming a second plurality of conductive interconnects on a second substrate (FIGS. 15-25, depicting wherein the first and second MIM capacitors 114a/114b are formed on interconnect layers 108b on each of the first and second substrates 102a/102b, respectively, [0070], [0072], [0027]); and forming a second plurality of 3D capacitors onto the second plurality of conductive interconnects and within respective ones of the plurality of pixel regions, wherein the second plurality of 3D capacitors respectively comprise a second base region and one or more second fingers extending outward from the second base region towards the second substrate (FIGS. 15-25, depicting wherein each of the MIM capacitors 114a/114b are formed on the interconnect layers 108b, each of the capacitors 114a/114b comprising a horizontal base region and fingers extending outward from the horizontal base region towards the respective substrates 102a/102b). Regarding the capacitors, in [0099], Takahashi states: “Accordingly, in some embodiments, the present disclosure relates to a high density MIM (metal-insulator-metal) capacitor that vertically extends over a plurality of conductive interconnect layers to provide for a high capacitance over a relatively small area.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed method of Lim by substituting the method of forming a capacitor of Takahashi in order to provide a capacitor having higher density, resulting in increased capacitance over a smaller area. See Takahashi [0099].
Regarding claim 30, Lim in view of Takahashi further discloses wherein the second plurality of 3D capacitors are respectively below one of the plurality of 3D capacitors (Lim FIGS. 12/13; Takahashi FIGS. 15-25; depicting wherein the second MIM capacitor 114b is below the first MIM capacitor 114a, such that the second MIM capacitor would be below the capacitors C1/C2).
Regarding claim 39, Lim does not specifically disclose forming a plurality of transistor devices within a second substrate; forming a plurality of conductive interconnects within a dielectric structure along a surface of the second substrate; and forming a second plurality of capacitors onto the plurality of conductive interconnects; and bonding the first substrate to the second substrate so that the second plurality of capacitors are within respective ones of the plurality of pixel regions.
In the same field of endeavor, Takahashi discloses a method of forming an image sensor, including steps of forming a 3D capacitor including steps of forming a plurality of transistor devices within a second substrate (FIGS. 15-25, depicting wherein the first and second MIM capacitors 114a/114b are formed on interconnect layers 108b and transistor devices 106 are formed on each of the first and second substrates 102a/102b, respectively, [0070], [0072], [0027], [0020]); forming a plurality of conductive interconnects within a dielectric structure along a surface of the second substrate (FIGS. 15-25, depicting interconnect layers 108b formed within ILD layers 202a, [0036]); and forming a second plurality of capacitors onto the plurality of conductive interconnects (FIGS. 15-25, depicting wherein the first and second MIM capacitors 114a/114b are formed on interconnect layers 108b and transistor devices 106 are formed on each of the first and second substrates 102a/102b, respectively); and bonding the first substrate to the second substrate (FIGS. 15-25, depicting wherein the first and second substrates 102a/102b are bonded at the bonding interface region 1404, [0068]). Regarding the capacitors, in [0099], Takahashi states: “Accordingly, in some embodiments, the present disclosure relates to a high density MIM (metal-insulator-metal) capacitor that vertically extends over a plurality of conductive interconnect layers to provide for a high capacitance over a relatively small area.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed method of Lim by substituting the method of forming a capacitor of Takahashi in order to provide a capacitor having higher density, resulting in increased capacitance over a smaller area. See Takahashi [0099].
Moreover, substitution of the capacitor configuration of Takahashi would result in a configuration wherein the second plurality of MIM capacitors 114b, which are stacked over the MIM capacitors 114a, are within respective ones of the plurality of unit pixels UP.
Regarding claim 40, Lim in view of Takahashi further discloses wherein the second plurality of capacitors are respectively below the plurality of capacitors (Lim FIGS. 12/13; Takahashi FIGS. 15-25; depicting wherein the second MIM capacitor 114b is below the first MIM capacitor 114a, such that the second MIM capacitors 114b would be below the capacitors C1/C2).
Regarding claim 41, Lim in view of Takahashi further discloses bonding the first substrate to the second substrate along a bonding interface that comprises a plurality of bond links and a plurality of dummy bond links (Lim FIGS. 12/13; Takahashi FIGS. 15-25, depicting wherein the first and second substrates 102a/102b are bonded along a bonding interface region 1404 comprising a plurality of bonding structures, e.g., 1408a/1408b and a plurality of dummy bond links in Lim, e.g., third wirings 252d/252f, [0068]), wherein the plurality of bond links are respectively and electrically coupled to the plurality of peripheral interconnect structures (Lim FIGS. 12/13; Takahashi FIGS. 15-25; depicting wherein the third wirings 252e and bonding structures 1408a/1408b are/would be electrically coupled to the vias 247/249).
Regarding claim 42, Lim in view of Takahashi further discloses wherein one of the plurality of bond links and one of the plurality of dummy bond links are respectively disposed within one of the plurality of pixel regions (Lim FIGS. 12/13; Takahashi FIGS. 15-25, depicting wherein the third wirings 252e and bonding structures 1408a/1408b are/would be disposed within one of the unit pixels UP).
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Takahashi.
Regarding claim 36, Choi does not specifically disclose forming a second plurality of interconnects on a second substrate; and forming a second 3D capacitor onto the second plurality of interconnects and within the pixel region, wherein the second 3D capacitor comprises a second base region and one or more second fingers extending outward from the second base region towards the second substrate.
In the same field of endeavor, Takahashi discloses a method of forming an image sensor, including steps of forming a 3D capacitor including steps of forming a second plurality of conductive interconnects on a second substrate (FIGS. 15-25, depicting wherein the first and second MIM capacitors 114a/114b are formed on interconnect layers 108b on each of the first and second substrates 102a/102b, respectively, [0070], [0072], [0027]); and forming a second plurality of 3D capacitors onto the second plurality of conductive interconnects and within respective ones of the plurality of pixel regions, wherein the second plurality of 3D capacitors respectively comprise a second base region and one or more second fingers extending outward from the second base region towards the second substrate (FIGS. 15-25, depicting wherein each of the MIM capacitors 114a/114b are formed on the interconnect layers 108b, each of the capacitors 114a/114b comprising a horizontal base region and fingers extending outward from the horizontal base region towards the respective substrates 102a/102b). Regarding the capacitors, in [0099], Takahashi states: “Accordingly, in some embodiments, the present disclosure relates to a high density MIM (metal-insulator-metal) capacitor that vertically extends over a plurality of conductive interconnect layers to provide for a high capacitance over a relatively small area.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed method of Choi by substituting the method of forming a capacitor of Takahashi in order to provide a capacitor having higher density, resulting in increased capacitance over a smaller area. See Takahashi [0099].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 20230067249 (published Mar. 2, 2023) (disclosing a 3D MIM capacitor configuration); 20160020270 (filed Oct. 1, 2015) (disclosing a 3D MIM capacitor coupled to a CMOS device); 20230041837 (published Feb. 9, 2023) (disclosing a 3D MIM capacitor configuration); 20220238636 (published July 28, 2022) (disclosing a 3D MIM capacitor configuration).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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