DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group I, claims 1-8 in the reply filed on 7/3/2026 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
3. The claims are objected because of the following reasons:
Re claim 4, line 5: in front of “storage node”, delete “a” and insert --the--.
Re claim 5, line 3: in front of “second gate”, delete “a” and insert --the--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 2, 4, 5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US 2023/0084611).
Re claim 1, Sato teaches, under BRI, Figs. 2-3, [0037, 0040, 0045], a random access memory comprising:
-a first transistor (220) including a first gate (G, 322) extending in a first direction (e.g., y- axis);
-a second transistor (210) including a second gate (G, 312) extending in a second direction (e.g., x-axis) perpendicular to the first direction and formed on an upper portion of the first transistor (220) (in flip view of Fig. 3); and
-a storage node (SN 230) configured to connect a first gate (312) of the first transistor (220) to a drain (D) of the second transistor (210) and storing data.
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Re claim 2, Sato teaches, [0016, 0038], wherein the first transistor (220) operates as a read transistor configured to read a state of the storage node (230), and the second transistor (210) operates as a write transistor configured to write data to the storage node (230).
Re claim 4, Sato teaches, Figs. 2-3, [0040, 0045, 0052], wherein the first transistor (220) includes a first drain contact (324-1) formed on one side of the first gate (322) to be parallel to the first gate (322), a first source contact (324-2) formed on the other side of the first gate (322) to be parallel to the first gate (322), a gate contact (326) formed on an upper portion of the first gate (322), and a storage node (SN 230) connecting the gate contact (324) to the drain (314-1) of the second transistor (210) in a straight line, the first drain contact (324-1) is connected to a read word line (RWL 224) extending in the second direction, and the first source contact (324-2) is connected to a read bit line (RBL 222) extending in the first direction.
Re claim 5, Sato teaches, Figs. 2-3, [0040, 0049, 0053], wherein the second transistor (210) includes, an interlayer separation layer (328) stacked on the upper portion of the first transistor (220), a second gate (312) formed on the interlayer separation layer (328), a second drain contact (314-1) formed on one side of the second gate (312), and a second source contact (314-2) formed on the other side of the second gate (312), a contact (326) of the second gate is connected to a write word line (WWL 214) extending in the second direction, and the second source contact (314-2) is connected to a write bit line (WBL 212) extending in the first direction.
Re claim 7, Sato teaches, Fig. 3, wherein a length of the first gate (322) is set independently of a length of the second gate (312).
5. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gardner et al. (US 2023/0019692).
Re claim 1, Gardner teaches, under BRI, Figs.16B, 18B & 20, [0126, 0131, 0133], a random access memory comprising:
-a first transistor (bottom transistor) including a first gate (250) extending in a first direction (e.g., y- axis);
-a second transistor (top transistor) including a second gate (254) extending in a second direction (e.g., x-axis) perpendicular to the first direction and formed on an upper portion of the first transistor (bottom transistor); and
-a storage node (2025) configured to connect a first gate (250) of the first transistor (bottom transistor) to a drain of the second transistor (top transistor) and storing data (2025).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chiang (US 2020/0135921).
The teachings of Sato have been discussed above.
Re claim 3, Sato does not explicitly teach wherein the first gate is formed of single crystal silicon, and the second gate is formed of one of polysilicon, low-temperature polysilicon, and an indium gallium zinc oxide (IGZO) material.
Chiang teaches, [0029], the first gate (103) is formed of single crystal silicon (e.g., monocrystalline), and the second gate (114) is formed of one of polysilicon (e.g., polysilicon), low-temperature polysilicon, and an indium gallium zinc oxide (IGZO) material.
As taught by Chiang, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first gate is formed of single crystal silicon, and the second gate is formed of one of polysilicon, low-temperature polysilicon, and an indium gallium zinc oxide (IGZO) material as claimed, because it aids in achieving multi-channel device with improved speed. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chiang in combination Sato due to above reason.
7. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Weber et al. (US 2018/0240874).
The teachings of Sato have been discussed above.
Re claim 8, Sato does not explicitly teach wherein the first transistor is formed as one of a planar field effect transistor (FET), a FinFET, a gate all around (GAA)-FET, a nanosheet (NS)-FET, a nanowire (NW)-FET, or a negative capacitance (NC)-FET, and the second transistor is formed as one of a tunnel FET (TFET), a recess channel array transistor (RCAT), or a saddle fin transistor.
Weber teaches “each of the first and second transistor is at least one of a field-effect transistor (FET), metal-oxide-semiconductor FET (MOSFET), tunnel-FET (TFET), finned configuration transistor, finFET configuration transistor, trigate configuration transistor, nanowire configuration transistor, nanoribbon configuration transistor, and gate-all-around configuration transistor” (claim 20).
As taught by Weber, one of ordinary skill in the art would utilize & modify the above teaching transistors to obtain the first transistor is formed as one of a planar field effect transistor (FET), a FinFET, a gate all around (GAA)-FET, a nanosheet (NS)-FET, a nanowire (NW)-FET, or a negative capacitance (NC)-FET, and the second transistor is formed as one of a tunnel FET (TFET), a recess channel array transistor (RCAT), or a saddle fin transistor as claimed, because it aids in achieving a desired transistor configuration with resistance reduction under transistor spacers.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Weber in combination Sato due to above reason.
Allowable Subject Matter
8. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takemura (US 2012/0287700, Figs. 1 & 2) discloses memory cell with two transistors and a capacitor.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/14/26
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