DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/5/2026 has been entered.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/1/2025, 8/7/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion", “on”, “between” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently discloses a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “a function word to indicate position in close proximity with” “in the intervening space” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang, Chih-Wei (US 2021/0407908 A1 hereinafter Huang) in view of Noh et al (US 2020/0381436 A1 hereinafter Noh) and further in view of Lin et al (US 10,497,704 B2 hereinafter Lin).
Regarding Claim 1, Huang discloses in Fig 2, 3A-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (aa) in a substrate (100) Fig 3A;
forming a trench (RS) in the substrate, wherein the trench has side surfaces and a bottom surface Fig 3B [0036];
forming a recess gate structure (104) in the substrate, wherein the recess gate structure intersects the active region (See Fig 3B);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (112/114: BC) in the atleast one dielectric layer;
forming a bit line (BL) over the bit line contact (BC) and in an additional dielectric layer (110c) Fig 3E;
forming a contact structure (112/114) on the substrate, wherein the contact structure is located at a side of the recess gate structure (104), and is electrically connected to the active region (AA);
sequentially forming a first conductive layer (108) and a second conductive layer (120) over the substrate, wherein the contact structure (112/114) is covered by the first and second conductive layers (See Fig 3G);
forming a conductive pillar (CP) and a landing pad (116) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3H, 3I); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3J);
wherein the recess gate structure is formed by:
oxidizing the side surfaces and the bottom surface the trench to conformally form a gate insulating layer (106), having a U-shaped configuration, in the trench at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0034-0044].
Huang does not disclose: forming a work function layer within the gate insulating layer and in the trench; forming a first conductive layer on the work function layer, within the gate insulating layer, and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein a top surface of the gate insulating layer is positioned below the top surface of the substrate.
However, Noh in a similar device teaches in Fig 6D-6H: forming a work function layer (124) on the gate insulating layer and in the trench;
forming a first conductive layer (126) on the work function layer, within the gate insulating layer, and in the trench; and
forming a capping layer (128) on the first conductive layer and in the trench;
[0029-0034].
References Huang and Noh are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang with the specified features of Noh because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Noh so that forming a work function layer within the gate insulating layer and in the trench; forming a first conductive layer on the work function layer, within the gate insulating layer, and in the trench; and forming a capping layer on the first conductive layer and in the trench as taught by Noh in Huang’s method since, this provides a novel technique for precisely controlling the threshold voltage of the gate electrode and enhancing the reliability of the integrated circuit device.
However, Lin in a similar device teaches in Fig 8: wherein a top surface of the gate insulating layer (22) is positioned below a top surface of the substrate (10).
References Huang, Noh and Lin are analogous art because they are directed to memory device processes and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang and Noh with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang, Noh and Lin so that a top surface of the gate insulating layer is positioned below a top surface of the substrate, as taught by Lin in Huang's and Noh’s method since, this eliminates the gate induced drain leakage problem (background).
Regarding Claim 2, Huang, Lin and Noh disclose: The method of claim 1, Huang discloses in Fig 2, 3A-3N: wherein the formation of the landing pad (116) is performed by a first etching process (Fig 3H, 3H) [0042].
Regarding Claim 3, Huang, Lin and Noh disclose: The method of claim 2, Huang discloses in Fig 2, 3A-3N: wherein the formation of the conductive pillar is performed by the first etching process and sequentially by a second etching process (Fig 3H, 3I) [0042].
Regarding Claim 4, Huang, Lin and Noh disclose: The method of claim 3, Huang discloses in Fig 2, 3A-3N: wherein the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process [0042, 0043] See Fig 3H, 3I.
Regarding Claim 5, Huang, Lin and Noh disclose: The method of claim 1, Huang discloses in Fig 2, 3A-3N: further comprising: forming a capacitor plug (PG) disposed over and electrically connected to the landing pad (CP) [0047].
Regarding Claim 6, Huang, Lin and Noh disclose: The method of claim 5, Huang discloses in Fig 2, 3A-3N: further comprising: forming a storage capacitor (SC) disposed over and electrically connected to the capacitor plug (Fig 3N) [0048].
Claims 1, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang, Chih-Wei (US 2021/0407908 A1 hereinafter Huang) in view of Lee et al (US 2017/0365608 A1 hereinafter Lee) and further in view of Lin et al (US 10,497,704 B2 hereinafter Lin).
Regarding Claim 1, Huang discloses in Fig 2, 3A-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (aa) in a substrate (100) Fig 3A;
forming a trench (RS) in the substrate, wherein the trench has side surfaces and a bottom surface [0036];
forming a recess gate structure (104) in the substrate, wherein the recess gate structure intersects the active region (See Fig 3B);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (112/114: BC) in the at least one dielectric layer;
forming a bit line (BL) over the bit line contact (BC) and in an additional dielectric layer (110c) Fig 3E;
forming a contact structure (112/114) on the substrate, wherein the contact structure is located at a side of the recess gate structure (104), and is electrically connected to the active region (AA);
sequentially forming a first conductive layer (108) and a second conductive layer (120) over the substrate, wherein the contact structure (112/114) is covered by the first and second conductive layers (See Fig 3G);
forming a conductive pillar (CP) and a landing pad (116) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3H, 3I); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3J);
wherein the recess gate structure is formed by:
oxidizing the side surfaces and the bottom surface the trench to conformally form a gate insulating layer (106), having a U-shaped configuration, in the trench at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0034-0044].
Huang does not disclose: forming a work function layer within the gate insulating layer and in the trench; forming a first conductive layer on the work function layer, within the gate insulating layer, and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein a top surface of the gate insulating layer is positioned below the top surface of the substrate.
However, Lee in a similar device teaches in Fig 10: forming a work function layer (146) on the gate insulating layer (120) and in the trench;
forming a first conductive layer (144) on the work function layer within the gate insulating layer, and in the trench; and
forming a capping layer (136) on the first conductive layer and in the trench;
wherein the word function layer (146), the first conductive layer (144), and the capping layer (136) are surrounded by the gate insulating layer (120) [0102].
References Huang and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Lee so that forming a work function layer within the gate insulating layer and in the trench; forming a first conductive layer on the work function layer, within the gate insulating layer, and in the trench; and forming a capping layer on the first conductive layer within the gate insulating layer and in the trench as taught by Lee in Huang’s method since, since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
However, Lin in a similar device teaches in Fig 8: wherein a top surface of the gate insulating layer (22) is positioned below a top surface of the substrate (10).
References Huang, Lee and Lin are analogous art because they are directed to memory device processes and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang and Lee with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang, Lee and Lin so that a top surface of the gate insulating layer is positioned below a top surface of the substrate, as taught by Lin in Huang's and Lee’s method since, this eliminates the gate induced drain leakage problem (background).
Regarding Claim 7, Huang, Lin and Lee disclose: The method of claim 1.
Huang and Lin do not disclose: wherein the recess gate structure further comprises:
conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer;
wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein; wherein the liner layer is in contact with the gate insulating layer.
However, Lee in a similar device teaches in Fig 10: wherein the recess gate structure further comprises: conformally disposing a liner layer (149_s) on the first conductive layer (144) and on the gate insulating layer (120), and disposed between the capping layer (136) and the first conductive layer (144); and disposing a second conductive layer (148) between the capping layer and the liner layer; wherein the liner layer (149_s) is formed in a U-shaped cross-sectional profile for the second conductive layer (148) disposing therein; wherein the liner layer is in contact (indirect contact) with the gate insulating layer (120) [0102].
References Huang, Lin and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang and Lin with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang, Lin and Lee so that the recess gate structure further comprises: conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer; wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein; wherein the liner layer is in contact with the gate insulating layer as taught by Lee in Huang’s and Lin’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Claim(s) 1, 7, 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Te-Yin (US 2021/0408005 A1 hereinafter Chen) in view of Huang, Tse-Yao (US 2024/0222370 A1 hereinafter Huang70) and further in view of Lin et al (US 10,497,704 B2 hereinafter Lin).
Regarding Claim 1, Chen discloses in Fig 2, 3A-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (aa) in a substrate (100) Fig 3A;
forming a trench (RS) in the substrate, wherein the trench has side surfaces and a bottom surface [0036];
forming a recess gate structure (104) in the substrate, wherein the recess gate structure intersects the active region (See Fig 3B);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (112/114: BC) in the at least one dielectric layer;
forming a bit line (BL) over the bit line contact (BC) and in an additional dielectric layer (110c) Fig 3E;
forming a contact structure (112/114) on the substrate, wherein the contact structure is located at a side of the recess gate structure (104), and is electrically connected to the active region (AA);
sequentially forming a first conductive layer (108) and a second conductive layer (120) over the substrate, wherein the contact structure (112/114) is covered by the first and second conductive layers (See Fig 3G);
forming a conductive pillar (CP) and a landing pad (116) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3H, 3I); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3J);
wherein the recess gate structure is formed by:
oxidizing the side surfaces and the bottom surface the trench to conformally form a gate insulating layer (106), having a U-shaped configuration, in the trench at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0034-0044].
Chen does not disclose: forming a work function layer within the gate insulating layer and in the trench; forming a first conductive layer on the work function layer, within the gate insulating layer, and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein a top surface of the gate insulating layer is positioned below a top surface of the substrate
However, Huang70 in a similar device teaches in Fig 1-16: forming a work function layer (313) on the gate insulating layer (311) and in the trench;
forming a first conductive layer (317) on the work function layer within the gate insulating layer and in the trench; and
forming a capping layer (323) on the first conductive layer and in the trench [0087-0089].
References Huang and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Huang with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang70 so that forming a work function layer on the gate insulating layer and in the trench; forming a first conductive layer on the work function layer within the gate insulating layer and in the trench; and forming a capping layer on the first conductive layer and in the trench as taught by Huang70 in Chen’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
However, Lin in a similar device teaches in Fig 8: wherein a top surface of the gate insulating layer (22) is positioned below a top surface of the substrate (10).
References Chen, Huang70 and Lin are analogous art because they are directed to memory device processes and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen and Huang70 with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Huang70 and Lin so that a top surface of the gate insulating layer is positioned below a top surface of the substrate, as taught by Lin in Chen's and Huang70’s method since, this eliminates the gate induced drain leakage problem (background).
Regarding Claim 7, Chen, Lin and Huang70 disclose: The method of claim 1.
Chen and Lin do not disclose: wherein the recess gate structure further comprises:
conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer;
wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein.
However, Huang70 in a similar device teaches in Fig 10: wherein the recess gate structure further comprises: conformally disposing a liner layer (319) on the first conductive layer (317) and on the gate insulating layer (311), and disposed between the capping layer (323) and the first conductive layer (317); and disposing a second conductive layer (321) between the capping layer and the liner layer; wherein the liner layer (319) is formed in a U-shaped cross-sectional profile for the second conductive layer (321) disposing therein [0059].
References Chen, Lin and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen, Lin with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Lin and Huang70 so that the recess gate structure further comprises: conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer; wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein as taught by Huang70 in Chen’s and Lin’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Regarding Claim 10, Chen, Lin and Huang70 disclose: The method of claim 7.
Chen and Lin do not disclose: wherein the liner layer is formed of a material having an etching selectivity to the gate insulating layer.
However, Huang70 in a similar device teaches in Fig 10: wherein the liner layer (319) is formed of a material having an etching selectivity to the gate insulating layer (311) [0059].
References Chen, Lin and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen and Lin with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Lin and Huang70 so that the liner layer is formed of a material having an etching selectivity to the gate insulating layer as taught by Huang70 in Chen’s and Lin’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Regarding Claim 11, Chen, Lin and Huang70 disclose: The method of claim 10.
Chen, Lin does not disclose: wherein the liner layer is formed of a material including sp² hybridized carbon atoms.
However, Huang70 in a similar device teaches in Fig 10: wherein the liner layer (319) is formed of a material including sp² hybridized carbon atoms [0061].
References Chen, Lin and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen and Lin with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Lin and Huang70 so wherein the liner layer is formed of a material including sp² hybridized carbon atoms as taught by Huang70 in Chen’s and Lin’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Regarding Claim 12, Chen, Lin and Huang70 disclose: The method of claim 7.
Chen and Lin do not disclose: wherein the second conductive layer is formed of molybdenum.
However, Huang70 in a similar device teaches in Fig 10: wherein the second conductive layer (321) is formed of molybdenum [0066].
References Chen, Lin and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen, Lin with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Lin and Huang70 so the second conductive layer is formed of molybdenum as taught by Huang70 in Chen’s and Lin’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Regarding Claim 13, Chen, Lin and Huang70 disclose: The method of claim 12.
Chen and Lin do not disclose: wherein the second conductive layer is formed by a chemical vapor deposition process.
However, Huang70 in a similar device teaches in Fig 10: wherein the second conductive layer (321) is formed by a chemical vapor deposition process [0066].
References Chen, Lin and Huang70 are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen and Lin with the specified features of Huang70 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen, Lin and Huang70 so that the second conductive layer is formed by a chemical vapor deposition process as taught by Huang70 in Chen and Lin’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim 1 but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 8, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein a width of the liner layer, a width of the conductive layer and a width of the word function layer are equal” as recited in claim 8 in combination with the remaining features.
Dependent claim 9 is indicated as allowable based on virtue of it’s dependency.
The most relevant prior art references, Chen, Te-Yin (US 2021/0408005 A1), Huang, Tse-Yao (US 2024/0222370 A1), Lin et al (US 10,497,704 B2) substantially teach the limitations of the claim 8, with the exception of the limitations described in the preceding paragraph.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811
