Prosecution Insights
Last updated: October 27, 2026

NANYA TECHNOLOGY Corporation

Technology area: Semiconductors, Circuits & Optics

116 pending office actions • 28 art units • 97 examiners • 0 of 116 (0%) have an AI response strategy ready • 324 patents granted in the last 365 days

Analysis

NANYA TECHNOLOGY Corporation has 118 pending office actions in Semiconductors, Circuits & Optics. The matters involve 99 examiners across 28 art units, indicating a very broad examiner network with substantial recurrence at the art-unit level.

MOJADDEDI, OMAR F is the busiest examiner, with 3 pending matters. The limited concentration at the busiest examiner means counsel should emphasize scalable prosecution processes, art-unit tracking, and consistent treatment of related semiconductor claim issues.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Portfolio Summary

116
Total Pending OAs
64
Non-Final OAs
52
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 15 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

4
Overdue
2
Due this week
3
Due this month
6
Due in next 60 days
0
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 15 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (4)Due ≤ 7 days (2)Due ≤ 30 days (3)Due ≤ 60 days (6)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

42
Hard (36%)
64
Medium (55%)
7
Easy (6%)
3
Unknown (3%)

Rejection Statute Mix

BucketCases
§101 + other1 (1%)
§103 only54 (47%)
§102 only7 (6%)
§112 only5 (4%)
Double-patenting only2 (2%)
Double-patenting + other3 (3%)
Multi-statute (no §101)41 (35%)
No statute on record3 (3%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

3
Life Sciences
3% of docket
4
Information Tech
3% of docket
2
Communications
2% of docket
101
Semiconductors
87% of docket
1
Mechanical / Eng
1% of docket
5
Business / Other
4% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

1,160 h
Manual time on pending OAs
232 h
Time saved (low, 20%)
406 h
Time saved (mid, 35%)
10.2 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
MOJADDEDI, OMAR F 3 89.6% +10.3%
RAHMAN, MOIN M 3 87.1% +14.0%
CRAWFORD EASON, LATANYA N 2 78.5% +0.4%
ARORA, AJAY 2 84.5% +6.8%
TRAN, TONY 2 70.2% +33.3%
MAZUMDER, DIDARUL A 2 86.6% +7.8%
VU, DAVID 2 77.3% +18.0%
BLACKWELL, ASHLEY NICOLE 2 97.3% -1.2%
BEARDSLEY, JONAS TYLER 2 61.0% +28.7%
FREY, KIMBERLY NEWMAN 2 75.8% +20.4%

Quick Wins (7)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 7 ordered by deadline are shown.

App #TitleExaminerDue in
18214662 SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR CARBON NANOTUBE AND MANUFACTURING METHOD THEREOF RAHMAN, MOIN M 33d
18769599 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING MULTILAYER MASK ARORA, AJAY —
18739600 SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME MAZUMDER, DIDARUL A —
18665856 SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME BLACKWELL, ASHLEY NICOLE —
18662012 SEMICONDUCTOR DEVICE WITH ANTIFERROELECTRIC SPACER LAYERS AND METHOD FOR FABRICATING THE SAME RAHMAN, MOIN M —
18648641 SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME BLACKWELL, ASHLEY NICOLE —
18443683 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME MOJADDEDI, OMAR F —

Hard Cases (42)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.

App #TitleExaminerDue in
17741593 MEMORY DEVICE HAVING PROTRUDING CHANNEL STRUCTURE LI, MEIYA 78d overdue
17879981 METAL STRUCTURE HAVING FUNNEL-SHAPED INTERCONNECT AND METHOD OF MANUFACTURING THE SAME LIN, JOHN 8d overdue
18326018 TEST SYSTEM AND TEST METHOD TO WAFERS LEE, HWA S 1d overdue
18129204 PROBING PAD DESIGN IN SCRIBE LINE FOR FLIP CHIP PACKAGE MULERO FLORES, ERIC MANUEL 7d
19231932 SEMICONDUCTOR STRUCTURE FOR DETECTING VERTICAL ELECTRICAL LEAKAGE KUPP, BENJAMIN MICHAEL —
18910338 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH LINER STRUCTURE MANDALA, MICHELLE —
18903246 CAPACITOR STRUCTURE AND METHOD FOR FABRICATING THE SAME RAMASWAMY, ARUN —
18882731 SEMICONDUCTOR DEVICE MIHALIOV, DMITRI —

Interview Candidates (14)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.

App #TitleExaminerDue in
18214662 SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR CARBON NANOTUBE AND MANUFACTURING METHOD THEREOF RAHMAN, MOIN M 33d
18237015 SEMICONDUCTOR DIE STUCTURE WITH AIR GAPS AND METHOD FOR PREPARING THE SAME BEARDSLEY, JONAS TYLER 41d
18765112 SEMICONDUCTOR STRUCTURE HAVING A MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME MOJADDEDI, OMAR F —
18763037 VERTICAL MEMORY STUCTURE WITH AIR GAPS AND METHOD FOR PREPARING THE SAME TRAN, TONY —
18739609 MEMORY DEVICE INCLUDING WORD LINE STRUCTURE HAVING LOWER AND UPPER GATE ELECTRODE LAYERS AND METHOD FOR PREPARING THE SAME VU, DAVID —
18739619 SEMICONDUCTOR DEVICE WITH ANTIFERROELECTRIC SPACER LAYERS AND METHOD FOR FABRICATING THE SAME RAHMAN, MOIN M —
18733103 SEMICONDUCTOR STRUCTURE HAVING A MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME MOJADDEDI, OMAR F —
18662012 SEMICONDUCTOR DEVICE WITH ANTIFERROELECTRIC SPACER LAYERS AND METHOD FOR FABRICATING THE SAME RAHMAN, MOIN M —

Top Art Units

Art UnitApps
2898 15
2893 11
2812 11
2818 9
2897 9
2811 8
2899 7
2817 6
2892 5
2813 3

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19262117 MEMORY MODULE AND METHOD FOR TESTING MEMORY MODULE BUTLER, SARAI E 2114 §103 Non-Final OA — Pending Jul 08, 2025
19231932 SEMICONDUCTOR STRUCTURE FOR DETECTING VERTICAL ELECTRICAL LEAKAGE KUPP, BENJAMIN MICHAEL 2893 §103§112Other Non-Final OA — Pending Jun 09, 2025
19071780 SYSTEM AND METHOD FOR TESTING MEMORY DEVICE YANG, HAN 2824 §112 Non-Final OA — Pending Mar 06, 2025
19055517 SYSTEM AND METHOD OF MEASURING FUSE RESISTANCE AND NON-TRANSITORY COMPUTER READABLE MEDIUM NGUYEN, HOAI AN D — §112Other Non-Final OA — Pending Feb 18, 2025
18987803 MEMORY-PAIRED SYSTEM FOR MULTIPLE STACKED SEMICONDUCTOR DEVICES AND REPAIR METHOD THEREOF LUU, PHO M 2824 §102 Non-Final OA — Pending Dec 19, 2024
18910338 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH LINER STRUCTURE MANDALA, MICHELLE 2893 §102§103 Non-Final OA — Pending Oct 09, 2024
18903246 CAPACITOR STRUCTURE AND METHOD FOR FABRICATING THE SAME RAMASWAMY, ARUN 2847 §102§103 Final Rejection — Pending Oct 01, 2024
18889659 CAPACITOR STRUCTURE MIYOSHI, JESSE Y 2898 §102 Non-Final OA — Pending Sep 19, 2024
18888460 SEMICONDUCTOR DEVICE WITH DIPOLE PORTION AND METHOD FOR PREPARING THE SAME SCHOENHOLTZ, JOSEPH 2893 DP Non-Final OA — Pending Sep 18, 2024
18888508 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME ABDELAZIEZ, YASSER A 2898 §102 Non-Final OA — Pending Sep 18, 2024
18886056 SEMICONDUCTOR DEVICE WITH DECOUPLING UNIT ANDREWS, FELIX BRYAN 2812 §103 Non-Final OA — Pending Sep 16, 2024
18883932 PACKAGE STRUCTURE INCLUDING AT LEAST TWO MEMORY DEVICES, ASSEMBLY STRUCTURE AND METHOD OF MANUFACTURING THE SAME CRAWFORD EASON, LATANYA N 2813 §103 Non-Final OA — Pending Sep 12, 2024
18883908 CONDUCTIVE STRUCTURE INCLUDING CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ELLIOTT, DANIEL KURT 2899 §102§103DP Non-Final OA — Pending Sep 12, 2024
18830995 OPTICAL SEMICONDUCTOR DEVICE WITH INTEGRATED VIAS IMPLEMENTING INTER-DIE CONNECTION OH, JAEHWAN — Other Non-Final OA — Pending Sep 11, 2024
18882731 SEMICONDUCTOR DEVICE MIHALIOV, DMITRI 2812 §102§103Other Non-Final OA — Pending Sep 11, 2024
18829235 WAFER CARRIER DRY CLEANER YUEN, JESSICA JIPING — §102§103§112 Non-Final OA — Pending Sep 09, 2024
18811749 MEMORY DEVICE AND METHOD FOR ADJUSTING SIGNAL TRANSMISSION BERMUDEZ LOZADA, ALFREDO 2825 §103 Non-Final OA — Pending Aug 21, 2024
18809362 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CRAWFORD EASON, LATANYA N — §102§103§112 Non-Final OA — Pending Aug 20, 2024
18805822 SEMICONDUCTOR DEVICE WITH SPACER AND METHOD FOR FABRICATING THE SAME DINKE, BITEW A 2812 §103 Non-Final OA — Pending Aug 15, 2024
18796383 SEMICONDUCTOR DEVICE WITH CATALYTIC CONDUCTIVE LAYER AND METHOD FOR FABRICATING THE SAME ARORA, AJAY 2892 §103§112Other Non-Final OA — Pending Aug 07, 2024
18770906 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SUPPORTING LAYER PHAM, HOAI V 2892 §102§103 Non-Final OA — Pending Jul 12, 2024
18769599 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING MULTILAYER MASK ARORA, AJAY 2892 §102 Non-Final OA — Pending Jul 11, 2024
18766956 SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME ALBRECHT, PETER M 2811 §112 Non-Final OA — Pending Jul 09, 2024
18765112 SEMICONDUCTOR STRUCTURE HAVING A MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME MOJADDEDI, OMAR F 2898 §102§103 Non-Final OA — Pending Jul 05, 2024
18765097 METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE HAVING FEATURES OF DIFFERENT DEPTHS MCCALL SHEPARD, SONYA D — §103 Non-Final OA — Pending Jul 05, 2024
18763037 VERTICAL MEMORY STUCTURE WITH AIR GAPS AND METHOD FOR PREPARING THE SAME TRAN, TONY 2893 §103 Final Rejection — Pending Jul 03, 2024
18755963 SEMICONDUCTOR DEVICE WITH PROGRAMMABLE STRUCTURE AND METHOD FOR FABRICATING THE SAME NGUYEN, SOPHIA T 2893 §102§103 Final Rejection — Pending Jun 27, 2024
18744946 MEMORY DEVICE HAVING MEMORY CELL WITH REDUCED PROTRUSION PARENDO, KEVIN A 2896 §112 Final Rejection — Pending Jun 17, 2024
18741826 WAREHOUSE ACCESS CONTROL SYSTEM AND METHOD OF OPERATING THE SAME STRAUB, D'ARCY WINSTON 2491 §103 Non-Final OA 34d Pending Jun 13, 2024
18742098 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME KARIMY, TIMOR 2818 §103 Non-Final OA — Pending Jun 13, 2024
18741149 PACKAGE STRUCTURE INCLUDING HEAT SINK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME NGUYEN, KHIEM D 2892 §102§103Other Final Rejection — Pending Jun 12, 2024
18740524 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF NGUYEN, NIKI HOANG 2818 §103§112 Non-Final OA — Pending Jun 12, 2024
18739600 SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME MAZUMDER, DIDARUL A 2812 §103 Final Rejection — Pending Jun 11, 2024
18739609 MEMORY DEVICE INCLUDING WORD LINE STRUCTURE HAVING LOWER AND UPPER GATE ELECTRODE LAYERS AND METHOD FOR PREPARING THE SAME VU, DAVID 2818 §103 Final Rejection — Pending Jun 11, 2024
18739619 SEMICONDUCTOR DEVICE WITH ANTIFERROELECTRIC SPACER LAYERS AND METHOD FOR FABRICATING THE SAME RAHMAN, MOIN M 2898 §101§103 Final Rejection — Pending Jun 11, 2024
18736859 SEMICONDUCTOR DEVICE STRUCTURE WITH STACKED CONDUCTIVE PLUGS AND METHOD FOR PREPARING THE SAME KUSUMAKAR, KAREN M 2897 §102§103 Non-Final OA — Pending Jun 07, 2024
18736847 OPTICAL SEMICONDUCTOR DEVICE WITH COMPOSITE INTERVENING STRUCTURE REAMES, MATTHEW L 2896 Other Final Rejection — Pending Jun 07, 2024
18733103 SEMICONDUCTOR STRUCTURE HAVING A MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME MOJADDEDI, OMAR F 2898 §102§103§112 Non-Final OA — Pending Jun 04, 2024
18676846 SYSTEMS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND RELEVANT METHODS JOH, CATHERINE 3723 §103 Final Rejection — Pending May 29, 2024
18675166 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF MOHAMED-ALY, KAREEM M 2898 §103 Non-Final OA — Pending May 28, 2024
18675156 SEMICONDUCTOR STRUCTURE MOTT, ADAM JOSEPH 2817 — Non-Final OA — Pending May 28, 2024
18674906 METHOD OF FORMING SEMICONDUCTOR STRUCTURE SANDVIK, BENJAMIN P 2812 §103 Non-Final OA — Pending May 26, 2024
18670918 PACKAGE STRUCTURE INCLUDING HEAT SINK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ARROYO, TERESA M 2893 §103 Final Rejection — Pending May 22, 2024
18668441 SEMICONDUCTOR DEVICE HAVING LANDING PAD AND METHOD FOR MANUFACTURING THE SAME HAIDER, WASIUL 2812 §102§103§112 Final Rejection — Pending May 20, 2024
18665856 SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME BLACKWELL, ASHLEY NICOLE 2897 §103 Final Rejection — Pending May 16, 2024
18664653 SEMICONDUCTOR DEVICE HAVING BIT LINE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME PARK, SAMUEL 2818 §103§112 Final Rejection — Pending May 15, 2024
18664628 METHOD AND APPARATUS FOR WAFER MEASUREMENT FREDERIKSEN, DAVID B 2858 §103 Final Rejection — Pending May 15, 2024
18662012 SEMICONDUCTOR DEVICE WITH ANTIFERROELECTRIC SPACER LAYERS AND METHOD FOR FABRICATING THE SAME RAHMAN, MOIN M 2898 §103 Final Rejection — Pending May 13, 2024
18655444 MEMORY DEVICE INCLUDING WORD LINE STRUCTURE HAVING LOWER AND UPPER GATE ELECTRODE LAYERS AND METHOD FOR PREPARING THE SAME VU, DAVID 2818 §103 Final Rejection — Pending May 06, 2024
18651931 METHOD FOR FORMING CONDUCTORS AND THEIR CONTACTS WHICH CARRY SIGNALS FOR ADVANCED SEMICONDUCTOR MEMORY DEVICES TYNES JR., LAWRENCE C 2899 §112 Non-Final OA — Pending May 01, 2024

View all 116 →

Managing NANYA TECHNOLOGY Corporation's Patent Portfolio?

IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.

Start Free Trial

Frequently Asked Questions

How many pending USPTO office actions does NANYA TECHNOLOGY Corporation have?

NANYA TECHNOLOGY Corporation has 116 pending office actions as of October 2026, spread across 28 art units and 97 examiners.

Which USPTO examiner handles the most NANYA TECHNOLOGY Corporation applications?

Omar F Mojaddedi has the most, with 3 of NANYA TECHNOLOGY Corporation's pending office actions.

What technology area are NANYA TECHNOLOGY Corporation's patent applications in?

Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month