Prosecution Insights
Last updated: April 19, 2026
Application No. 18/635,364

SEMICONDUCTOR MEMORY DEVICE PERFORMING REFRESH OPERATION

Final Rejection §102§103§112
Filed
Apr 15, 2024
Examiner
BEGUM, SULTANA
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
1y 11m
To Grant
94%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
486 granted / 522 resolved
+25.1% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
32 currently pending
Career history
554
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 522 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claim(s) to be treated in this office action: a. Independent: 1, 16 and 20 b. Pending: 1-20 Claims 1-3, 7, 13-15 and 20 has been amended. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Specification The new title is reviewed and accepted by examiner. Paragraph [0015] amendments are reviewed and accepted by examiner. Claim Objections Claim 20 objection is withdrawn pursuant to addition of punctuation mark. Claim Rejections - 35 USC § 112 Claim 1-15 rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn pursuant to claim amendments. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20220352880). Regarding independent claim 1, Chen discloses an apparatus (Figs. 4A-4B) comprising: a plurality of input signal lines respectively paired with a plurality of output signal lines (Fig. 4A and [0034] describes a data transmission path 470 connected at the input end to the output of the driving buffer 410. Here for simplicity, only one path is shown); a plurality of first delay circuits operatively connected between the plurality of input signal lines and the plurality of output signal lines (Fig. 4B and [0033] describes a number of delay elements 422, 424, 426, 428); and a first selector circuit configured to connect a selected one of the plurality of first delay circuits between a selected one of the plurality of input signal lines and a respective one of the plurality of output signal lines (Fig. 4B and [0036] describes multiplexer 430 that connects few of the first delay circuits between input and corresponding output signal lines). Regarding claim 2, Chen discloses all the elements of claim 1 as above and further a number of the plurality of first delay circuits is less than a number of the plurality of input signal lines (Fig. 4B shows number of delay circuits (422, 424, 426 and 428) is 4 and there are 5 input signal lines. one for each of the plane 410a, 410b, 410c, 410d and 410e). Regarding claim 3, Chen discloses all the elements of claim 2 as above and further the first selector circuit is configured to select one of the plurality of first delay circuits responsive to a first selection signal (Fig. 3 shows selector 326 selects delay circuit 310 from one of the rows based on selection signal CODE) and select one of the plurality of input signal lines and the respective one of the output signal lines responsive to a second selection signal (Fig. 4B and [0033] describes that selector inputs DT0 and DT1 selects one of the inputs of the multiplexer as the output of the multiplexer 430. Thus, the output of the multiplexer 430 is the input to the delay cell 420 delayed by one, two, three, or four delay elements 422, 424, 426, 428, depending on the setting of the selector inputs DT0 and DT1). Regarding claim 13, Chen discloses all the elements of claim 2 as above and further the first selector circuit is configured to connect a first one of the plurality of first delay circuits between a first one of the plurality of input signal lines and a respective first one of the plurality of output signal lines in a first operation timing, and wherein the first selector circuit is configured to connect the first one of the plurality of first delay circuits between a second one of the plurality of input signal lines and a respective first one of the plurality of output signal lines in a second operation timing (Figs. 4A-4B along with [0033]-[0034]). Regarding claim 14, Chen discloses all the elements of claim 13 as above and further the first selector circuit is configured to connect a second one of the plurality of first delay circuits between the first one of the plurality of input signal lines and the respective first one of the plurality of output signal lines in a third operation timing (Figs. 4A-4B along with [0033]-[0034] describes the option of selecting different delay circuits within the same input and output pair which will result a different operation timing). Regarding claim 15, Chen discloses all the elements of claim 2 as above and further a connection relation between the plurality of first delay circuits and the plurality of input signal lines is dynamically changed responsive to a selection signal (Figs. 4A-4B and [0033]-[0034] describes that based on selection signals DT0 and DT1, relation between the plurality of first delay circuits and the plurality of input signal lines is dynamically changed). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20220352880) in view of Xu et al. (US 7348821). Regarding claim 4, Chen discloses all the elements of claim 3 as above and through Xu further the first selection signal is updated each time a predetermined command is issued from outside (Fig. 1 and (18) describes that selector 126 responds to the external command CODE to select a selected delayed signal from the DL0, DL1, DL2, and DL3 signals. Also Fig. 3 and (30)). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Xu to Chen in order to provide with selected delayed signal which may be fed to a second circuit for use as a timing or control signal. The second circuit may need timing or control signals with different delays relative to each other as taught by Xu (113). Allowable Subject Matter Claims 16-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Independent claim 16 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having gate connections and control signal connections as recited. Claims 5-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection rely on newly found reference Chen et al. (US 20220352880). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/26/2026
Read full office action

Prosecution Timeline

Apr 15, 2024
Application Filed
Nov 05, 2025
Non-Final Rejection — §102, §103, §112
Feb 17, 2026
Response Filed
Feb 26, 2026
Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603121
MEMORY REFRESH WITH NEGATIVE VOLTAGE GENERATOR
2y 5m to grant Granted Apr 14, 2026
Patent 12597457
INITIAL SETTING DEVICE OF SEMICONDUCTOR MEMORY TO DETERMINE VALID SETTING
2y 5m to grant Granted Apr 07, 2026
Patent 12592276
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER THAT OPERATES FOR TWO DIFFERENT VOLTAGE RANGE AND WRITING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12592272
MEMORY DEVICE HAVING NON-UNIFORM REFRESH
2y 5m to grant Granted Mar 31, 2026
Patent 12580008
POWER GATING CIRCUIT WITH MEMORY PRECHARGE SUPPORT
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
94%
With Interview (+0.4%)
1y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 522 resolved cases by this examiner. Grant probability derived from career allow rate.

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