Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed January 27th, 2026 has been entered. Claims 1-10, 12, and 14-20 are pending in this application. Applicant’s amendments to the claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed October 1st, 2025.
The amendments made to independent claims 1, 12, and 17 include additional limitations directed to performing an extra sensing operation not required to sense the data, using the results of the extra sensing operation in logic operations on error bits to identify memory cells in upper and lower tails of threshold voltage distributions, and adjusting threshold voltages of the identified memory cells towards centers of respective threshold voltage distributions.
Response to Arguments
Applicant’s arguments, see pgs. 11-12, filed January 27th, 2026, with respect to the rejection(s) of claims 1-10, 12, and 14-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kurose et al. (US 2021/0357289), hereinafter Kurose, in view of Lee et al. (US 9,183,924), hereinafter Lee, and further in view of Lo et al. (US 8,526,240), hereinafter Lo.
Applicant argues that the cited prior art, alone of in combination, does not teach or suggest the amended limitations of claim 1, including "at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in tails of threshold voltage distributions", and "adjusting threshold voltages of the identified memory cells to be closer to centers of respective threshold voltages distributions without changing threshold voltages distributions for the identified memory cells."
Examiner acknowledges Applicant’s position that the prior art of record does not explicitly teach or suggest the above-recited limitations. As discussed during the interview, Examiner performed an updated search. Accordingly, the prior art of record is not relied upon for the newly added limitations, and a new grounds of rejection have been made (see below).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kurose, in view of Lee, and further in view of Lo.
Regarding claim 1, Kurose teaches a non-volatile storage apparatus, comprising: a set of non-volatile memory cells; and a control circuit connected to the non-volatile memory cells, the control circuit is configured to: read a page of data from the set of non-volatile memory cells (Kurose, Abstract, lines 1-5, "A memory system includes a semiconductor storage device and a memory controller including a storage circuit... and a control circuit that reads data from the memory cells") including performing multiple sensing operations on the set of non-volatile memory cells, the multiple sensing operations comprise one or more sensing operations to sense the page of data (Kurose, Fig. 6, step S11, para. [0096], lines 4-8, "Specifically, in step S11, the CPU 31 causes the semiconductor storage device 10 to perform read operations of a lower page and an upper page. The read voltage based on the correction value table is used in the read operations"; para. [0086], lines 2-9, "one page data (lower page data) configured with lower bits is determined by a read operation using the read voltage BR. One page data (upper page data) configured with upper bits is determined by a read operation using each of the read voltages AR and CR. In a page read operation in which a plurality of read voltages are used, the logic circuit LC appropriately performs an operation process"; the read operation of the page data equates to a sensing operation) and performing an extra sensing operation not required to sense the page of data (Kurose, para. [0127]-[0129] teaches a read retry for adjusting read reference voltages, this implies additional sensing operations beyond the initial sensing operation for reading the page of data), perform an error correction process on the page of data read (Kurose, Abstract, lines 4-9, "performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count"), identify first error bits based on the error correction process, the first error bits identify bits in the sensed page of data that were sensed as a first result but should be a second result, identify second error bits based on the error correction process, the second error bits identify bits in the sensed page of data that were sensed as the second result but should be the first result (Kurose, para. [0115]-[0117], “In (b) and (c) of FIG. 8, the state corresponding to the data of ‘1’ and ‘0’ is denoted by a solid line, and the other state is denoted by a dashed line. Further, in (b) and (c) of FIG. 8, the overlapping portion between two adjacent states are illustrated independently. As illustrated in (b) of FIG. 8, in the state corresponding to the data of ‘1’, data of the memory cell transistor MT whose threshold voltage is higher than or equal to the read voltage VCG is a fail bit. The fail bit changed from the data of ‘1’ to the data of ‘0’ by the error correction process is detected and corrected to the data. As illustrated in (c) of FIG. 8, in the state corresponding to the data of ‘0’, data of the memory cell transistor MT whose threshold voltage is lower than the read voltage VCG is a fail bit. The fail bit changed from the data of ‘0’ to the data of ‘1’ by the error correction process is detected and corrected to the data of ‘0’”), perform one or more logic operations (Kurose, para. [0072], lines 1-7, "The logic circuit LC performs various logic operations by using data stored in the latch circuits SDL, ADL, BDL and XDL connected to the common bus LBUS. Specifically, the logic circuit LC can perform an AND operation, an OR operation, a NAND operation, a NOR operation, an EXNOR operation, and the like by using the data stored in the two latch circuits") on the first error bits with one or more of the results of the multiple sensing operations and perform one or more logic operations on the second error bits with one or more results of the multiple sensing operations to identify memory cells in the set of non-volatile memory cells that are in tails of threshold voltage distributions (Kurose, para. [0119], lines 1-8, "When the memory cell transistor MT stores a plurality of bits of data, the CPU 31 can specify the type of fail bit detected by the error correction process by combining the data before error correction and the data after the error correction. When the MLC method is used, the upper tail fail bit TFB and the lower tail fail bit BFB between the two adjacent states are associated with each other…"). Kurose teaches performing sensing operations and determining error bits, and processing the error bits to identify memory cells that are associated with errors, which equates to memory cells located in tail regions of threshold voltage distributions. Since the error correction process taught in para. [0115]-[0119] is performed on data obtained from the sensing operations, the results from the sensing operations are inherently used in the logic operations on the error bits to identify memory cells associated with the upper and lower tails of threshold voltage distributions.
Kurose fails to teach at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in tails of threshold voltage distributions, and adjust the memory cells that are identified to be in the tails of the threshold voltage distributions by adjusting threshold voltages of the identified memory cells to be closer to centers of respective threshold voltages distributions without changing threshold voltages distributions for the identified memory cells.
However, Lee, in an analogous art, teaches, and at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in tails of threshold voltage distributions (Lee, col. 1, lines 42-47, “errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells in a nonvolatile memory device may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors”; the plurality of reading operations equates to multiple sensing operations and the decoding equates to logic operations on the sensing results).
Kurose and Lee are both considered to be analogous to the claimed invention because both are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kurose to incorporate the teachings of Lee since the decoding operations taught in Lee operates on data obtained from the plurality of reading operations, the results of the sensing operations are used in logic operations to identify memory cells. Combining this with Kurose’s teaching of first and second error bits and tail fail bits would have been obvious to use results of sensing operations and logic operations on error bits to identify memory cells located in the tails of threshold voltage distributions.
The suggestion/motivation for doing so would be to improve the accuracy of identifying memory cells with errors.
The combination of Kurose in view of Lee, taken singly or combined, fails to adjust the memory cells that are identified to be in the tails of the threshold voltage distributions by adjusting threshold voltages of the identified memory cells to be closer to centers of respective threshold voltages distributions without changing threshold voltages distributions for the identified memory cells.
However, Lo, in an analogous art, teaches adjust the memory cells that are identified to be in the tails of the threshold voltage distributions by adjusting threshold voltages of the identified memory cells to be closer to centers of respective threshold voltages distributions without changing threshold voltages distributions for the identified memory cells (Lo, Abstract, lines 5-7, “A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell”; Fig. 4 teaches adjusting programming voltages based on how memory cell voltages compare to a verify voltage; adjusting programming voltages toward a target verify voltage equates to moving threshold voltages of memory cells towards centers of respective threshold voltage distributions without changing the overall threshold voltage distributions, since only the individual memory cells are adjusted, rather than shifting the entire distribution).
Kurose, Lee and Lo are considered to be analogous to the claimed invention because they are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee to incorporate the teachings of Lo by including the functionality of adjusting the threshold voltages of error-prone cells.
The suggestion/motivation for doing so would be to improve reliability and reduce errors.
Regarding claim 2, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the error correction process failed (Kurose, Fig. 6, step S13, para. [0097], lines 6-8, "If the error correction process by the ECC circuit 34 is completed, the CPU 31 checks whether or not the error correction is successful [step S13]"); and the control circuit is further configured to the perform one or more logic operations in response to determining that the error correction process failed. Kurose teaches performing an error correction process to determine error bits and also teaches performing logic operations using a logic circuit on data. Since logic operations are performed on data resulting from the error correction process, the logic operations are performed in response to determining that errors exist in the data, which equates to determining that the error correction process failed and performing one or more logic operations in response to the determination.
Regarding claim 3, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to perform one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations and perform one or more logic operations on the second error bits with one or more results of the multiple sensing operations to identify memory cells in upper tails and lower tails of the overlapping threshold voltages distributions (Lee, col. 1, lines 42-47, “errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells in a nonvolatile memory device may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the Kurose to incorporate the teachings of Lee since the decoding operations taught in Lee operates on data obtained from the plurality of reading operations, the results of the sensing operations are used in logic operations to identify memory cells. Combining this with Kurose’s teaching of first and second error bits and tail fail bits would have been obvious to use results of sensing operations and logic operations on error bits to identify memory cells located in the tails of threshold voltage distributions.
The suggestion/motivation for doing so would be to improve the accuracy of identifying memory cells with errors.
Regarding claim 4, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 3, wherein the control circuit is configured to adjust the memory cells by: lowering threshold voltages of memory cells that are identified to be in upper tails; and raising threshold voltages of memory cells that are identified to be in the lower tails (Kurose, para. [0129]-[0130], "As such, the fail bit count FBC tends to decrease, for example, as the fail ratio RAT approaches 1. Further, when the read voltage is shifted in a positive direction, it is considered that the lower tail fail bit count BFBC increases and the upper tail fail bit count TFBC decreases, and when the read voltage is shifted in a negative direction, it is considered that the lower tail fail bit count BFBC decreases and the upper tail fail bit count TFBC increases. [0130] Accordingly, the shift amount of the read voltage is set in the positive direction when the fail ratio RAT is smaller than 1, and is set in the negative direction when the fail ratio RAT is larger than 1. Furthermore, the shift amount of the read voltage is set so as to increase as the fail ratio RAT goes away from 1. For example, when RAT=0.1, the read voltage is shifted by +5 DAC. When RAT=0.5, the read voltage is shifted by +3 DAC. When RAT=l, the read voltage is not shifted. When RAT=2, the read voltage is shifted by -3 DAC. When RAT=l0, the read voltage is shifted by -5 DAC").
Regarding claim 5, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 4, wherein: the control circuit is configured to raise threshold voltages of memory cells that are identified to be in the lower tails by programming memory cells including applying a series of voltage pulses that increase in voltage magnitude pulse-to-pulse from a starting magnitude such that the starting magnitude is different for different target overlapping threshold voltages distributions (Lo, Fig. 6 teaches different verify voltages and adjusting the programming voltage depending on the threshold result).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee to incorporate the teachings of Lo by including the functionality of the control circuitry raising threshold voltages in the lower tails by applying voltage pulses that increase in voltage magnitude.
The suggestion/motivation for doing so would be to raise threshold voltages of memory cells in lower tail regions, to the desired voltage level and improve reliability, as well as reduce errors.
Regarding claim 7, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the set of non-volatile memory cells are configured to store multiple bits of data in multiple pages of data (Kurose, para. [0119] teaches storing multiple data bits); the set of non-volatile memory cells are configured to be in threshold voltages distributions corresponding to multiple data states (Kurose, para. [0127]-[0131] teaches adjusting read reference voltages corresponding to various data states); and the one or more sensing operations to sense the page of data comprise a sensing at one read reference voltage for one data state and a sensing at another read reference voltage for another data state (Kurose, para. [0132]-[0133] teaches sensing operations being performed for each read voltage and shift amounts being calculated for each the read voltages for each state).
Regarding claim 12, Kurose teaches a method comprising: reading a data set from a set of non-volatile memory cells in overlapping threshold voltages distributions (Kurose, para. [0119]-[0129] teaches an MLC method, threshold voltage distributions, and the use of multiple read reference voltages to gather fail bit counts) including performing multiple sensing operations on the set of non-volatile memory cells (Kurose, para. [0127]-[0129] teaches reading using multiple read reference voltages), the multiple sensing operations comprise one or more sensing operations to sense the set of data (Kurose, Fig. 6, step S11, para. [0096], lines 4-8, "Specifically, in step S11, the CPU 31 causes the semiconductor storage device 10 to perform read operations of a lower page and an upper page. The read voltage based on the correction value table is used in the read operations"; para. [0086], lines 2-9, "one page data (lower page data) configured with lower bits is determined by a read operation using the read voltage BR. One page data (upper page data) configured with upper bits is determined by a read operation using each of the read voltages AR and CR. In a page read operation in which a plurality of read voltages are used, the logic circuit LC appropriately performs an operation process"; the read operation of the page data equates to a sensing operation) and performing an extra sensing operation not required to sense the set of data (Kurose, para. [0127]-[0129] teaches a read retry for adjusting read reference voltages, this implies additional sensing operations beyond the initial sensing operation for reading the page of data); performing an error correction process on the of data set (Kurose, Fig. 11, step S24, para. [0141], lines 1-3, “Then, the CPU 31 causes the ECC circuit 34 to perform an error correction process for the read result of the shift read [step S24]”); determining that the data set was not read successfully (Kurose, para. [0097], lines 6-8, “If the error correction process by the ECC circuit 34 is completed, the CPU 31 checks whether or not the error correction is successful [step S13]”); and in response to determining that the data set was not read successfully: identifying first error bits as a result of the error correction process, the first error bits identify bits in the sensed page of data that were sensed as a first value but should be a second value; identifying second error bits as a result of the error correction process, the second error bits identify bits in the sensed page of data that were sensed as the second value but should be the first value (Kurose, para. [0120]-[0126] identifies upper and lower error bits after error correction); performing one or more logic operations (Kurose, para. [0072], lines 1-7, "The logic circuit LC performs various logic operations by using data stored in the latch circuits SDL, ADL, BDL and XDL connected to the common bus LBUS. Specifically, the logic circuit LC can perform an AND operation, an OR operation, a NAND operation, a NOR operation, an EXNOR operation, and the like by using the data stored in the two latch circuits") on the first error bits with one or more results of the multiple sensing operations and performing one or more logic operations on the second error bits with one or more results of the multiple sensing operations to identify memory cells in upper tails and lower tails of the overlapping threshold voltages distributions (Kurose, para. [0120]-[0126] teaches classifying fail bits as upper or lower tail based on sensing results; para. [0119], lines 1-8, "When the memory cell transistor MT stores a plurality of bits of data, the CPU 31 can specify the type of fail bit detected by the error correction process by combining the data before error correction and the data after the error correction. When the MLC method is used, the upper tail fail bit TFB and the lower tail fail bit BFB between the two adjacent states are associated with each other…"; Kurose does not explicitly teach the limitation but by combining error-bits with sensing results to identify tail cells implies using Boolean logic such as an AND operation to filter the cells). Kurose teaches performing sensing operations and determining error bits, and processing the error bits to identify memory cells that are associated with errors, which equates to memory cells located in tail regions of threshold voltage distributions. Since the error correction process taught in para. [0115]-[0119] is performed on data obtained from the sensing operations, the results from the sensing operations are inherently used in the logic operations on the error bits to identify memory cells associated with the upper and lower tails of threshold voltage distributions).
Kurose fails to teach at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in upper tails and lower tails of threshold voltage distributions and adjusting threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells.
However, Lee, in an analogous art, teaches at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in upper tails and lower tails of threshold voltage distributions (Lee, col. 1, lines 42-47, “errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells in a nonvolatile memory device may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors”; the plurality of reading operations equates to multiple sensing operations and the decoding equates to logic operations on the sensing results).
Kurose and Lee are both considered to be analogous to the claimed invention because both are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kurose to incorporate the teachings of Lee since the decoding operations taught in Lee operates on data obtained from the plurality of reading operations, the results of the sensing operations are used in logic operations to identify memory cells. Combining this with Kurose’s teaching of first and second error bits and tail fail bits would have been obvious to use results of sensing operations and logic operations on error bits to identify memory cells located in the tails of threshold voltage distributions.
The suggestion/motivation for doing so would be to improve the accuracy of identifying memory cells with errors.
The combination of Kurose in view of Lee, taken singly or combined, fails to teach adjusting threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells
However, Lo, in an analogous art, teaches adjusting threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells (Lo, Abstract, lines 5-7, “A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell”; Fig. 4 teaches adjusting programming voltages based on how memory cell voltages compare to a verify voltage; adjusting programming voltages toward a target verify voltage equates to moving threshold voltages of memory cells towards centers of respective threshold voltage distributions without changing the overall threshold voltage distributions, since only the individual memory cells are adjusted, rather than shifting the entire distribution).
Kurose, Lee and Lo are considered to be analogous to the claimed invention because they are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee, to incorporate the teachings of Lo by including the functionality of adjusting the threshold voltages of error-prone cells.
The suggestion/motivation for doing so would be to improve reliability and reduce errors.
Regarding claim 14, the combination of Kurose in view of Lee, and further in view of Lo teaches the method of claim 12, wherein: the set of non-volatile memory cells are configured to store multiple bits of data each in multiple pages of data (Kurose, para. [0119], lines 1-2, “When the memory cell transistor MT stores a plurality of bits of data…”); the set of non-volatile memory cells are configured to be in threshold voltages distributions corresponding to multiple data states (Kurose, Figs. 15-19 teaches threshold voltage distributions corresponding to various states); and the data set is a page of data (Kurose, Fig. 6, step S11 teaches page read operations).
Claim 15 is a method with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 16 is a method with limitations similar to the apparatus of claim 7, and is rejected under the same rationale.
Regarding claim 17, Kurose teaches a non-volatile storage apparatus, comprising: a set of non-volatile memory cells; and a control circuit connected to the non-volatile memory cells (Kurose, Abstract, lines 1-5, "A memory system includes a semiconductor storage device and a memory controller including a storage circuit... and a control circuit that reads data from the memory cells"), the control circuit is configured to:
read a data set from the set of non-volatile memory cells pre-programmed to be in overlapping threshold voltages distributions (Kurose, para. [0119]-[0129] teaches an MLC method, threshold voltage distributions, and the use of multiple read reference voltages to gather fail bit counts) including performing multiple sensing operations on the set of non-volatile memory cells (Kurose, para. [0127]-[0129] teaches reading using multiple read reference voltages), the multiple sensing operations comprise one or more sensing operations to sense the set of data (Kurose, Fig. 6, step S11, para. [0096], lines 4-8, "Specifically, in step S11, the CPU 31 causes the semiconductor storage device 10 to perform read operations of a lower page and an upper page. The read voltage based on the correction value table is used in the read operations"; para. [0086], lines 2-9, "one page data (lower page data) configured with lower bits is determined by a read operation using the read voltage BR. One page data (upper page data) configured with upper bits is determined by a read operation using each of the read voltages AR and CR. In a page read operation in which a plurality of read voltages are used, the logic circuit LC appropriately performs an operation process"; the read operation of the page data equates to a sensing operation) and performing an extra sensing operation not required to sense the set of data (Kurose, para. [0127]-[0129] teaches a read retry for adjusting read reference voltages, this implies additional sensing operations beyond the initial sensing operation for reading the page of data); performing an error correction process on the of data set (Kurose, Fig. 11, step S24, para. [0141], lines 1-3, “Then, the CPU 31 causes the ECC circuit 34 to perform an error correction process for the read result of the shift read [step S24]”), identify first error bits, the first error bits identify bits in the sensed page of data that were sensed as a first value but should be a second value; identify second error bits, the second error bits identify bits in the sensed page of data that were sensed as the second value but should be the first value (Kurose, para. [0120]-[0126] identifies upper and lower error bits after error correction); perform one or more logic operations (Kurose, para. [0072], lines 1-7, "The logic circuit LC performs various logic operations by using data stored in the latch circuits SDL, ADL, BDL and XDL connected to the common bus LBUS. Specifically, the logic circuit LC can perform an AND operation, an OR operation, a NAND operation, a NOR operation, an EXNOR operation, and the like by using the data stored in the two latch circuits") on the first error bits with one or more results of the multiple sensing operations and perform one or more logic operations on the second error bits with one or more results of the multiple sensing operations to identify memory cells in upper tails and lower tails of the overlapping threshold voltages distributions (Kurose, para. [0120]-[0126] teaches classifying fail bits as upper or lower tail based on sensing results; para. [0119], lines 1-8, "When the memory cell transistor MT stores a plurality of bits of data, the CPU 31 can specify the type of fail bit detected by the error correction process by combining the data before error correction and the data after the error correction. When the MLC method is used, the upper tail fail bit TFB and the lower tail fail bit BFB between the two adjacent states are associated with each other…"; Kurose does not explicitly teach the limitation but by combining error-bits with sensing results to identify tail cells implies using Boolean logic such as an AND operation to filter the cells). Kurose teaches performing sensing operations and determining error bits, and processing the error bits to identify memory cells that are associated with errors, which equates to memory cells located in tail regions of threshold voltage distributions. Since the error correction process taught in para. [0115]-[0119] is performed on data obtained from the sensing operations, the results from the sensing operations are inherently used in the logic operations on the error bits to identify memory cells associated with the upper and lower tails of threshold voltage distributions).
Kurose fails to teach at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in upper tails and lower tails of threshold voltage distributions and adjust threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells.
However, Lee, in an analogous art, teaches at least a subset of the one or more logic operations on the first error bits and the one or more logic operations on the second error bits use results of the extra sensing operation to identify memory cells in the set of non-volatile memory cells that are in upper tails and lower tails of threshold voltage distributions (Lee, col. 1, lines 42-47, “errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells in a nonvolatile memory device may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors”; the plurality of reading operations equates to multiple sensing operations and the decoding equates to logic operations on the sensing results).
Kurose and Lee are both considered to be analogous to the claimed invention because both are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kurose to incorporate the teachings of Lee since the decoding operations taught in Lee operates on data obtained from the plurality of reading operations, the results of the sensing operations are used in logic operations to identify memory cells. Combining this with Kurose’s teaching of first and second error bits and tail fail bits would have been obvious to use results of sensing operations and logic operations on error bits to identify memory cells located in the tails of threshold voltage distributions.
The suggestion/motivation for doing so would be to improve the accuracy of identifying memory cells with errors.
The combination of Kurose in view of Lee, taken singly or combined, fails to teach adjust threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells.
However, Lo, in an analogous art, teaches adjust threshold voltages of the identified memory cells to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells (Lo, Abstract, lines 5-7, “A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell”; Fig. 4 teaches adjusting programming voltages based on how memory cell voltages compare to a verify voltage; adjusting programming voltages toward a target verify voltage equates to moving threshold voltages of memory cells towards centers of respective threshold voltage distributions without changing the overall threshold voltage distributions, since only the individual memory cells are adjusted, rather than shifting the entire distribution).
Kurose, Lee and Lo are considered to be analogous to the claimed invention because they are in the same field of memory cell programming.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee to incorporate the teachings of Lo by including the functionality of adjusting the threshold voltages of error-prone cells.
The suggestion/motivation for doing so would be to improve reliability and reduce errors.
Claim 18 is an apparatus with limitations similar to the apparatus of claim 2, and is rejected under the same rationale.
Claim 19 is an apparatus with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 20 is an apparatus with limitations similar to the apparatus of claim 6, and is rejected under the same rationale.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kurose in view of Lee, and further in view of Lo, as applied to claim 3 above, and further in view of Jeon (US 9,741,402).
Regarding claim 6, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 3, but fails to teach wherein the control circuit is configured to adjust the memory cells by: lowering threshold voltages of memory cells that are identified to be in upper tails to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions; and raising threshold voltages of memory cells that are identified to be in the lower tails to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions.
However, Jeon, in an analogous art, teaches wherein the control circuit is configured to adjust the memory cells by: lowering threshold voltages of memory cells that are identified to be in upper tails to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions; and raising threshold voltages of memory cells that are identified to be in the lower tails to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions (Jeon, col. 1, lines 40-49, “The controller determines whether a reference voltage is positioned in a selected threshold voltage distribution, based on section cell numbers, and determines to adjust the reference voltage, in the case where the reference voltage not positioned in the selected threshold voltage distribution. The controller sets a new reference voltage by adjusting, using a predetermined offset value, an average threshold voltage of a threshold voltage distribution adjacent to the selected threshold voltage distribution corresponding to the reference voltage”).
Kurose, Lee, Lo and Jeon are considered to be analogous to the claimed invention because they are in the same field of memory systems that utilize threshold voltage distribution.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee, and further in view of Lo, to incorporate the teachings of Jeon by including the functionality of lowering or raising threshold voltages in the upper and lower tails, respectively.
The suggestion/motivation for doing so would be to improve the performance of the device by adjusting read voltages to be closed to the optimal read voltage, which will cause a reduction in error bits (Jeon, col. 8, lines 62-64, “The optimal read voltages may be voltages for minimizing error bits included in data read from the memory cells”).
Claim 8-10 is rejected under 35 U.S.C. 103 as being unpatentable over Kurose in view of Lee, and further in view of Lo, as applied to claim 1 above, and further in view of Sharon et al., hereinafter Sharon (US 8,873,288).
Regarding claim 8, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the set of non-volatile memory cells are configured to store three bits of data each in three pages of data; the set of non-volatile memory cells are configured to be in threshold voltages distributions corresponding to a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state and an eight data state (Kurose, para. [0119]-[0126] teaches an MLC method and a plurality of data states); the one or more sensing operations to sense the page of data comprise a sensing at a second read reference voltage for the second data state and sensing at a sixth read reference voltage for the sixth data state (Kurose, para. [0127]-[0129] teaches sensing at different read reference voltages and adjusting read voltages based on fail-bit counts); the extra sensing operation comprises sensing at an additional voltage level between the second read reference voltage and the sixth read reference voltage (Kurose, para. [0127]-[0129]; while not explicitly taught, this limitation is implied by the adjusting of the read reference voltages); the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations (Kurose, para. [0122]-[0126] teaches the controller identifying first error bits and using the sensing results to classify them as upper tail fail bits TFB or lower tail fail bits BFB); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations (Kurose, para. [0122]-[0126]).
The combination of Kurose in view of Lee, and further in view of Lo fails to teach the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the second read reference voltage for the second data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the second data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the sixth read reference voltage for the fifth data state to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the fifth data state; and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the additional voltage level to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the first data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the additional voltage level to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the sixth data.
However, Sharon teaches the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the second read reference voltage for the second data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the second data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the sixth read reference voltage for the fifth data state to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the fifth data state (Sharon, Fig. 39, col. 45, lines 1-17, “FIG. 39 again considers the states of FIGS. 30 and 32, but with the four voltages shown labeled V1, V2, V3 and V4 for the present discussion. Further, consider these four voltages applied in the set of four sensing operations illustrated in FIG. 40. Here, a first sensing operation respectively applies the voltages V1, V2, V3 and V4 to the word lines WL0, WL2, WL4 and WL6. The result of the first sensing operation is '1' in those bit lines that satisfy: (Vth0≤V1) AND (Vth2≤V2) AND (Vth4≤V3) AND (Vth6≤V4) (Condition 1) Where Vth0, Vth2,Vth4 and Vth6 are the threshold voltages of the cells in WLs 0, 2, 4 and 6, respectively. The four sensing voltages are then cycled as shown for the second, third and fourth sensing operations, where similar conditions apply to the second, third and fourth sensing operations”); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the additional voltage level to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the first data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the additional voltage level to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the sixth data state (Sharon, Fig. 39, col. 45, lines 1-17). While Sharon does not explicitly teach the limitations, Sharon teaches performing a AND operation across sense results to isolate cells that meet multiple conditions. A person of ordinary skill in the art would know that the natural way to map error bits to sense results is with a bitwise AND operation.
Kurose, Lee, Lo and Sharon are considered to be analogous to the claimed invention because they are in the same field of memory systems that utilize threshold voltage distribution.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee, and further in view of Lo to incorporate the teachings of Sharon by including the functionality of performing a bitwise AND operations between the error bits and bitwise indication of memory cells that were turned on/off in response to sensing voltage results.
The suggestion/motivation for doing so would be that logical operations, such as bitwise AND operations, are routine implementation methods for filtering data and would have yielded the expected results.
Regarding claim 9, the combination of Kurose in view of Lee, further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the set of non-volatile memory cells are configured to store three bits of data each in three pages of data; the set of non-volatile memory cells are configured to be in threshold voltages distributions corresponding to a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state and an eight data state (Kurose, para. [0119]-[0126] teaches an MLC method and a plurality of data states); the one or more sensing operations to sense the page of data comprise a sensing at a fourth read reference voltage for the fourth data state and sensing at an eighth read reference voltage for the eighth data state; (Kurose, para. [0127]-[0129] teaches sensing at different read reference voltages and adjusting read voltages based on fail-bit counts); the extra sensing operation comprises sensing at an additional voltage level between the fourth read reference voltage and the eighth read reference voltage (Kurose, para. [0127]-[0129]; while not explicitly taught, this limitation is implied by the adjusting of the read reference voltages); the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations (Kurose, para. [0122]-[0126] teaches the controller identifying first error bits and using the sensing results to classify them as upper tail fail bits TFB or lower tail fail bits BFB); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations (Kurose, para. [0122]-[0126]).
The combination of Kurose in view of Lee, and further in view of Lo fails to teach the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the fourth read reference voltage for the fourth data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the fourth data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the eighth read reference voltage for the eighth data state to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the seventh data state; and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the additional voltage level to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the third data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the additional voltage level to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the eighth data state.
However, Sharon teaches the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the fourth read reference voltage for the fourth data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the fourth data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the eighth read reference voltage for the eighth data state to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the seventh data state (Sharon, Fig. 39, col. 45, lines 1-17, “FIG. 39 again considers the states of FIGS. 30 and 32, but with the four voltages shown labeled V1, V2, V3 and V4 for the present discussion. Further, consider these four voltages applied in the set of four sensing operations illustrated in FIG. 40. Here, a first sensing operation respectively applies the voltages V1, V2, V3 and V4 to the word lines WL0, WL2, WL4 and WL6. The result of the first sensing operation is '1' in those bit lines that satisfy: (Vth0≤V1) AND (Vth2≤V2) AND (Vth4≤V3) AND (Vth6≤V4) (Condition 1) Where Vth0, Vth2,Vth4 and Vth6 are the threshold voltages of the cells in WLs 0, 2, 4 and 6, respectively. The four sensing voltages are then cycled as shown for the second, third and fourth sensing operations, where similar conditions apply to the second, third and fourth sensing operations”); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the additional voltage level to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the third data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the additional voltage level to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the eighth data state (Sharon, Fig. 39, col. 45, lines 1-17). While Sharon does not explicitly teach the limitations, Sharon teaches performing a AND operation across sense results to isolate cells that meet multiple conditions. A person of ordinary skill in the art would know that the natural way to map error bits to sense results is with a bitwise AND operation.
Kurose, Lee, Lo and Sharon are considered to be analogous to the claimed invention because they are in the same field of memory systems that utilize threshold voltage distribution.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee, and further in view of Lo to incorporate the teachings of Sharon by including the functionality of performing a bitwise AND operations between the error bits and bitwise indication of memory cells that were turned on/off in response to sensing voltage results.
The suggestion/motivation for doing so would be that logical operations, such as bitwise AND operations, are routine implementation methods for filtering data and would have yielded the expected results.
Regarding claim 10, the combination of Kurose in view of Lee, and further in view of Lo teaches the non-volatile storage apparatus of claim 1, wherein: the set of non-volatile memory cells are configured to store three bits of data each in three pages of data; the set of non-volatile memory cells are configured to be in threshold voltages distributions corresponding to a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state and an eight data state (Kurose, para. [0119]-[0126] teaches an MLC method and a plurality of data states); the one or more sensing operations to sense the page of data comprise a sensing at a third read reference voltage for the third data state, sensing at an fifth read reference voltage for the fifth data state and sensing at a seventh read reference voltage for the seventh data state; (Kurose, para. [0127]-[0129] teaches sensing at different read reference voltages and adjusting read voltages based on fail-bit counts); the extra sensing operation comprises sensing at a fourth read reference voltage for the fourth data state and sensing at a sixth read reference voltage for the sixth data state (Kurose, para. [0127]-[0129]; while not explicitly taught, this limitation is implied by the adjusting of the read reference voltages); the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations (Kurose, para. [0122]-[0126] teaches the controller identifying first error bits and using the sensing results to classify them as upper tail fail bits TFB or lower tail fail bits BFB); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations (Kurose, para. [0122]-[0126]).
The combination of Kurose in view of Lee, and further in view of Lo fails to teach the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the third read reference voltage for the third data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the third data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the sixth read reference voltage for the sixth data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the seventh data state; and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the fourth read reference voltage to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the second data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the seventh read reference voltage to identify memory cells in the upper tail of the threshold voltages distribution corresponding to the sixth data state.
However, Sharon teaches the one or more logic operations on the first error bits with one or more of the results of the multiple sensing operations comprising a bitwise AND operation between the first error bits and bitwise indication of memory cells that turned on in response to sensing at the third read reference voltage for the third data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the third data state, and a bitwise AND operation between the first error bits and bitwise indication of memory cells that did not turn on in response to sensing at the sixth read reference voltage for the sixth data state to identify memory cells in a lower tail of the threshold voltages distribution corresponding to the seventh data state (Sharon, Fig. 39, col. 45, lines 1-17, “FIG. 39 again considers the states of FIGS. 30 and 32, but with the four voltages shown labeled V1, V2, V3 and V4 for the present discussion. Further, consider these four voltages applied in the set of four sensing operations illustrated in FIG. 40. Here, a first sensing operation respectively applies the voltages V1, V2, V3 and V4 to the word lines WL0, WL2, WL4 and WL6. The result of the first sensing operation is '1' in those bit lines that satisfy: (Vth0≤V1) AND (Vth2≤V2) AND (Vth4≤V3) AND (Vth6≤V4) (Condition 1) Where Vth0, Vth2,Vth4 and Vth6 are the threshold voltages of the cells in WLs 0, 2, 4 and 6, respectively. The four sensing voltages are then cycled as shown for the second, third and fourth sensing operations, where similar conditions apply to the second, third and fourth sensing operations”); and the one or more logic operations on the second error bits with one or more results of the multiple sensing operations comprising a bitwise AND operation between the second error bits and bitwise indication of memory cells that turned on in response to sensing at the fourth read reference voltage to identify memory cells in an upper tail of the threshold voltages distribution corresponding to the second data state, and a bitwise AND operation between the second error bits and bitwise indication of memory cells that did not turn on in response to sensing at the seventh read reference voltage to identify memory cells in the upper tail of the threshold voltages distribution corresponding to the sixth data state (Sharon, Fig. 39, col. 45, lines 1-17). While Sharon does not explicitly teach the limitations, Sharon teaches performing a AND operation across sense results to isolate cells that meet multiple conditions. A person of ordinary skill in the art would know that the natural way to map error bits to sense results is with a bitwise AND operation.
Kurose, Lee, Lo and Sharon are considered to be analogous to the claimed invention because they are in the same field of memory systems that utilize threshold voltage distribution.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kurose in view of Lee, and further in view of Lo to incorporate the teachings of Sharon by including the functionality of performing a bitwise AND operations between the error bits and bitwise indication of memory cells that were turned on/off in response to sensing voltage results.
The suggestion/motivation for doing so would be that logical operations, such as bitwise AND operations, are routine implementation methods for filtering data and would have yielded the expected results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Watanabe et al. (US 6,657,897) teaches adjusting a threshold voltage of a memory cell transistors to various threshold voltage levels.
Kim et al. (US 2012/0269003) teaches multiple verification operations and identifying unreliable memory cells.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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