DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 16 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The closest relevant prior art of record, Song et al. (U.S. PG Pub. # 2021/0223478 A1), fails to teach or suggest fourth and fifth trenches as claimed.
Claims 21 – 34 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The closest relevant prior art of record, Song et al. (U.S. PG Pub. # 2021/0223478 A1), teaches the p-doped (30) and n-doped (32) regions on either side of an intrinsic region (26’), thus making the junction a p-i-n junction. Thus, ‘478 fails to teach or disclose that a PN junction being formed as claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (U.S. PG Pub. # 2021/0223478 A1).
In Re claims 15 and 20, ‘478 teaches a method for forming an integrated circuit device, comprising: forming a first oxide layer (20b) over a substrate (20a); forming a semiconductor layer (26) on the first oxide layer, the semiconductor layer comprising a first semiconductor material (silicon, par. 0016); forming a first trench and a second trench (either side of 26b) parallel to the first trench in the semiconductor layer; filling the first trench and the second trench with an oxide material (42); forming a first n-doped region (32) and a first p-doped region (30) adjacent the first n- doped region in the semiconductor layer between and parallel to the first trench and the second trench; forming a third trench (44) along and into the first n-doped region and the first p-doped region (fig. 5), the third trench comprising a proximal region (bottom of 44), a tapered region (middle of 44), and a distal region (top of 44) arranged in order along the first n-doped region and the first p-doped region, wherein: the proximal region has a first width laterally (horizontal) transverse to the first trench and the second trench (vertical depths); the distal region has a second width laterally transverse to the first trench and the second trench, the second width greater than the first width (fig. 5); and the tapered region has a width that linearly increases from a first end adjacent the proximal region to a second end adjacent the distal region (fig. 5); and filling the third trench with a second semiconductor material (46, germanium).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
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/CHAD H SMITH/Primary Examiner, Art Unit 2874
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