Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 6, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 7, 9, 14
b. Pending: 1-2, 4-9, 11-14, 16-20
Claims 1, 7, 9, and 14 have been amended and claims 3, 10, and 15 have been canceled.
Response to Arguments
Applicant's arguments filed January 6, 2026 have been fully considered but they are not persuasive. Examiner has found claim 2 rejectable using Mokhlesi, and therefore claim 9 is also rejectable using Mokhlesi, since it contains mostly the same subject matter as claim 1.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 2 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The subject matter of claim 2 is entirely encompassed by the new limitation added to claim 1, specifically the third limitation of claim. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 8-9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mokhlesi (US Pub. 20080084754 A1).
Regarding independent claim 1, Mokhlesi discloses a method of operating a memory device (the circuit in figure 4), comprising the steps of:
preparing a plane (100, figure 3) that includes a plurality of memory blocks (there are three block of cell 30 in figure 3) that are in electrical communication with a plurality of bit lines (27, figure 3);
performing a first read operation (read the first block as shown in para 0121, and figure 23) on a first memory block (namely the upper block 30 in figure 3) of the plurality of memory blocks (as above) while a plurality of bit lines (27, figure 3) are held at a first voltage (the voltage applied to selected bit line B, figure 9) that is greater than zero Volts (260 is greater than 0 V);
without ramping the plurality of bit lines down from the first voltage (the voltage applied to selected bit line B, figure 9), performing a second read operation (the read data in selected bit line C, figure 9) on a second memory block of the plurality of memory blocks (as above; it is noted that the voltage applied to the first read in first block of cell is not ramping when the second block of cell is selected to be read); and
wherein during the steps of performing the first read operation and performing the second read operation, the plurality of bit lines do not fall by more than 25% from the first voltage (above, it is noted that Mokhlesi teaches a voltage applied to the first block of cells which does not ramp. Examiner concludes that if there is no ramping of the bit line voltage, it follows that “the plurality of bit lines do not fall by more than 25% from the first voltage”).
Regarding claim 2, Mokhlesi discloses the limitations of claim 1, and further:
wherein during and between the steps of performing the first read operation and performing the second read operation, the plurality of bit lines do not fall by more than 25% from the first voltage (as above; see the rejection of the last limitation of claim 1).
Regarding claim 5, Mokhlesi discloses the limitations of claim 1, and further:
wherein the memory device (the circuit in figure 4) is a first memory device (100, 104A, 104B, figure 4) of a plurality of memory devices, the plurality of memory devices (104A, 104B, 100,figure 4) being in electrical communication with a processor unit (144, figure 4).
Regarding claim 6, Mokhlesi discloses the limitations of claim 5, and further:
wherein the plurality of memory devices (100, 104A, 104B, 130A, figure 4) that are in electrical communication with the processor unit (144, figure 4) includes at least four memory devices (100, 104A, 104B, 130A, figure 4) that are of similar construction to the first memory device (as above).
Regarding claim 8, Mokhlesi discloses the limitations of claim 1, and further:
wherein the first (the first read operation in the first block as explained above) and second read operations (the second read in the second block as explained above) both include only a single reference voltage (the bit line voltage applied to the selected bit line is single reference voltage) for reading data programmed according to a single bit per memory cell storage scheme.
Independent claim 9 is mostly the same in claimed subject matter as claim 1 except for being drafted in device format instead of method format and is rejected for the same reasons as independent claim 1.
Regarding claim 11, Mokhlesi discloses the limitations of claim 9, and further:
claim 9, wherein the first (the upper block 30, figure 3) and second memory blocks (the middle block in figure 3) are different memory blocks in the plane (100, figure 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (US Pub. 20080084754 A1) in view of Oh (US Pat. 11177005 B2).
Regarding claim 4, Mokhlesi discloses the limitations of claim 1. Mokhlesi does not disclose:
wherein the plane including the plurality of memory blocks is a first plane and the plurality of memory blocks is a first plurality of memory blocks, and
wherein the memory device further includes a second plane with a second plurality of memory blocks, the second plane being able to operate in parallel with the first plane.
However, Oh teaches:
the plane (Plane A, figure 7) including the plurality of memory blocks (BLKl, BLK2, figure 7) is a first plane (Plane A, figure 7) and the plurality of memory blocks is a first plurality of memory blocks (as above), and
wherein the memory device further includes a second plane (Plane 2, figure 7) with a second plurality of memory blocks (BLKn, figure 7), the second plane (as above) being able to operate in parallel (PlaneA and Plane Bin figure 7 are parallel) with the first plane (Plane A, figure 7).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oh to Mokhlesi wherein the plane including the plurality of memory blocks is a first plane and the plurality of memory blocks is a first plurality of memory blocks, and wherein the memory device further includes a second plane with a second plurality of memory blocks, the second plane being able to operate in parallel with the first plane in order to improve the degree of integration and the by increasing the number of cell strings per block (Oh, column 16, lines 3-6) and improve efficiency by performing erase in units of a sub-block (Oh, column 16, lines 26-35).
Regarding claim 12, Mokhlesi discloses the limitations of claim 9. Claim 12 recites mostly the same limitations as claim 4 and henceforth is rejected for the same reasons.
Claims 14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (US Pub. 20080084754 A1) in view of Wong et al. (US Pat. 6278633 B1; “Wong”).
Regarding independent claim 14, Mokhlesi discloses all limitations of this claim (see the rejection applied to claim 1) except for the recitation of the use of a plurality of high bandwidth flash units for storing data.
Wong teaches a memory device that includes a high bandwidth flash unit (see title) for storing data in a memory device.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Wong to modified Mokhlesi wherein the plane including the plurality of memory blocks is a first plane and the plurality of memory blocks is a first plurality of memory blocks, and wherein the memory device further includes a second plane with a second plurality of memory blocks, the second plane being able to operate in parallel with the first plane in order to improve the accuracy of write operations by adjusting programming parameters based on evaluations (Wong, column 5, lines 12-15).
Regarding claim 19, Mokhlesi and Wong together disclose all the limitations of claim 14, and further through Wong:
wherein the plurality of high bandwidth flash units includes at least four high bandwidth flash units that are constructed similarly to one another (Fig. 1: pipelines 110-1 to 110-N; col. 5, lines 16-23).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Wong to modified Mokhlesi wherein the plurality of high bandwidth flash units includes at least four high bandwidth flash units that are constructed similarly to one another in order to improve the accuracy of write operations by adjusting programming parameters based on evaluations (Wong, column 5, lines 12-15).
Regarding claim 20, Mokhlesi and Wong together disclose all the limitations of claim 14. Claim 20 recites exactly the same limitations as claim 8 and henceforth is rejected for the same reasons.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (US Pub. 20080084754 A1) and Wong (US Pat. 6278633 B1) as applied to claim 14 above, and further in view of Oh (US Pat. 11177005 B2).
Regarding claim 16, Mokhlesi and Wong together disclose all the limitations of claim 14. Neither Mokhlesi nor Wong disclose:
wherein the first and second memory blocks are different memory blocks in the same plane.
However, Oh teaches:
wherein the first and second memory blocks are different memory blocks (Blkl, BLK2, figure 7) in the same plane (Plane A, figure 7).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oh to modified Mokhlesi wherein the first and second memory blocks are different memory blocks in the same plane in order to improve the degree of integration and the by increasing the number of cell strings per block (Oh, column 16, lines 3-6) and improve efficiency by performing erase in units of a sub-block (Oh, column 16, lines 26-35).
Regarding claim 17, Mokhlesi and Wong together disclose all the limitations of claim 14. Neither Mokhlesi nor Wong disclose:
wherein the control circuitry is configured to operate the plurality of planes in parallel.
However, Oh teaches:
wherein the control circuitry (130A, figure 7) is configured to operate the plurality of planes (see figure 7) in parallel.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oh to modified Mokhlesi wherein the control circuitry is configured to operate the plurality of planes in parallel in order to improve the degree of integration and the by increasing the number of cell strings per block (Oh, column 16, lines 3-6) and improve efficiency by performing erase in units of a sub-block (Oh, column 16, lines 26-35).
Allowable Subject Matter
Claim 7 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 7 includes allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
“without ramping the plurality of bit lines down from the first voltage, performing a third read operation on a third memory block of the plurality of memory blocks, the third memory block being different than the first and second memory blocks.”
The Examiner was not able to find additional references to logically combine with Mokhlesi, Wong, and Oh in order to reject the other above features of claim 7. Refer to conclusion section for relevant references.
Claims 13 and 18 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mun (US Pub. 20140036599 A1): para. [0053] and Fig. 6 are relevant to claims 1, 7, 9, and 14.
Wang et al. (US Pub. 20220254417 A1): paras. [0047]-[0048], [0056], [0058], [0064], claims 10-11, and Figs. 11, and 14-18 are relevant to claims 1, 7, 9, and 14.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
3/16/2026