DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement mailed on 06/17/2026, the Applicant elected Group I (claims 1-18) in a reply filed on 08/04/2026. Applicant requests the examiner to consider rejoinder of withdrawn claims 19-20, because independent claim 19 includes the recitations of claim 10. The examiner respectfully disagrees.
Claims 1-18 of Group I drawn to an electronic device, classified in H10W90/701 and claims 19-20 of Group II drawn to a method of manufacturing an electronic device, classified in H10W70/04. Groups II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). As a non-limiting example, the device can be made by another and materially different process than the process as recited in claims 19-20. For example, the electronic device can be made by forming the interposer structure including the interposer dielectric layer and the interposer conductive layer before forming the under layer with the under layer aperture on the interposer structure, rather than forming the under layer before forming the interposer structure including the interposer dielectric layer and the interposer conductive layer, then coupling the under layer with the interposer structure as recited in claims 19-20.
Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply: the inventions have acquired a separate status in the art in view of their different classification, the inventions have acquired a separate status in the art due to their recognized divergent subject matter, and/or the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Therefore, the requirement is still deemed proper and is therefore made FINAL.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 19-20 of the non-elected Group II are withdrawn.
Currently, claims 1-18 are examined as below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 14/977,977, filed on 12/22/2015.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 08/06/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Having an Interposer Including a Reinforcement Layer
(Clean Version) Semiconductor Device Having an Interposer Including a Reinforcement Layer
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 is indefinite, because the limitation “the lower signal distribution structure couples the interconnection structure the interposer conductive layer bottom side” renders the claim indefinite. It is unclear whether the lower signal distribution structure couples the interconnection structure and the interposer conductive layer bottom side, or the lower signal distribution structure couples the interconnection structure or the interposer conductive layer bottom side. The limitation will be interpreted as the lower signal distribution structure couples the interconnection structure and the interposer conductive layer bottom side, for the purpose of examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0225258 A1 to Chiu et al. (“Chiu”).
PNG
media_image1.png
630
737
media_image1.png
Greyscale
Regarding independent claim 1, Chiu in Fig. 6D teaches an electronic device 16 (Fig. 6D & ¶ 60, semiconductor device 16) comprising:
an under layer 41 (¶ 60, first passivation layer 41) comprising a mold material 41 (¶ 29, first passivation layer 41 is the same as the passivation layer 22; ¶ 19, the passivation layer 22 includes epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), which is a mold material1. In other words, the first passivation 41 comprises a mold material), wherein the under layer 41 includes an under layer top side (Fig. 6D, top side of the layer 41), an under layer bottom side (Fig. 6D, bottom side of the layer 41), and an under layer aperture (Fig. 6D, ¶ 30, opening formed through the first passivation layer 41 that exposes a portion of the metal line 36) that extends between the under layer top side and the under layer bottom side (Fig. 6D);
an interposer 30 (¶ 60, interconnecting structure 30 including layers 32, 36, 38 and 40) comprising an interposer top side (Fig. 6D, top side of the interposer 30), an interposer lateral side (Fig. 6D, lateral side of the interposer 30), an interposer bottom side (Fig. 6D, bottom side of the interposer 30) coupled to the under layer top side (Fig. 6D), an interposer dielectric layer 38 (Fig. 6D, ¶ 20, the lowermost inter-metal dielectric (IMD) 38) at the interposer bottom side, and an interposer conductive layer 36 (Fig. 6D, ¶ 20, metal line 36) at the interpose bottom side, wherein at least a portion of an interposer conductive layer bottom side 36 (Fig. 6D, ¶ 20, the lowermost metal line 36) is exposed by the under layer aperture (Fig. 6D, ¶ 30);
an interconnection structure 50A (¶ 60, connector 50A) electrically coupled to the interposer conductive layer bottom side 36 through the under layer aperture (Fig. 6D); and
a first semiconductor die 54 (¶ 68, die 54) electrically coupled to the interposer 30 (Fig. 6D, ¶ 68).
Regarding claim 2, Chiu in Fig. 6D further teaches a second semiconductor die 54 (¶ 33, die 54 comprising multiple stacked dies) electrically coupled to the interposer 30 (Fig. 6D, ¶ 33).
Regarding claim 3, Chiu in Fig. 2D further teaches the first semiconductor die 54 vertically covers a first portion of the interposer 30 (Fig. 6D, ¶ 33, one of the multiple stack dies 54 would cover a portion of the interposer 30); and
the second semiconductor die 54 vertically covers a second portion of the interposer 30 (Fig. 6D, ¶ 33, the other one of the multiple stack dies 54 would cover a portion of the interposer 30).
Regarding claim 4, Chiu in Fig. 6D further teaches an upper dielectric layer 22 (¶ 19, passivation layer 22 including silicon nitride or silicon oxide or low-k dielectric) and an upper conductive layer 50B (¶ 68, connector 50B) on the interposer top side (Fig. 6D); and
wherein the first semiconductor die 54 is electrically coupled to the interposer 30 through the upper conductive layer 50 (Fig. 6D, ¶ 68, ¶ 17).
Regarding claim 5, Chiu in Fig. 6D further teaches the interconnection structure 50A comprises a conductive ball or a conductive bump (¶ 34).
Regarding claim 6, Chiu in Fig. 6D further teaches a lower signal distribution structure 46A (¶ 60, ¶ 17, under bump metallization (UBM) 46A) on the under layer bottom side (Fig. 6D).
Regarding claim 7, Chiu in Fig. 6D further teaches the lower signal distribution structure 46A couples the interconnection structure 50A the interposer conductive layer bottom side 36 (Fig. 6D).
Regarding claim 8, Chiu in Fig. 6D further teaches the lower signal distribution structure 46A comprises a plating 46A (¶ 60, ¶ 32).
Regarding claim 9, Chiu in Fig. 6D further teaches the plating 46A is laterally wider than the under layer aperture (Fig. 6D).
Regarding independent claim 10, Chiu in Fig. 6D teaches an electronic device 16 (Fig. 6D & ¶ 60, semiconductor device 16) comprising:
an under layer 41 (¶ 60, first passivation layer 41) of a mold material 41 (¶ 29, first passivation layer 41 is the same as the passivation layer 22; ¶ 19, the passivation layer 22 includes epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), which is a mold material2. In other words, the first passivation 41 comprises a mold material), wherein the under layer 41 includes an under layer top side (Fig. 6D, top side of the layer 41), an under layer bottom side (Fig. 6D, bottom side of the layer 41), and an under layer aperture (Fig. 6D, ¶ 30, opening formed through the first passivation layer 41 that exposes a portion of the metal line 36) that extends between the under layer top side and the under layer bottom side (Fig. 6D);
an interposer dielectric layer 38 (Fig. 6D, ¶ 20, inter-metal dielectric (IMD) 38) comprising an interposer dielectric layer top side (Fig. 6D, top side of the uppermost IMD 38) and an interposer dielectric layer bottom side (Fig. 6D, bottom side of the lowermost IMD 38), wherein the interposer dielectric layer bottom side outwardly faces the under layer top side and is coupled to the under layer 41 via the under layer top side (Fig. 6D);
an interposer conductive layer 36 (Fig. 6D, ¶ 20, metal line 36) comprising an interposer conductive layer top side (Fig. 6D, top side of the uppermost layer 36) and an interposer conductive layer bottom side (Fig. 6D, bottom side of the lowermost layer 36), and wherein at least a portion of the interposer conductive layer bottom side is exposed by the under layer aperture (Fig. 6D);
an upper dielectric layer 22 (¶ 19, passivation layer 22 including silicon nitride or silicon oxide or low-k dielectric) and an upper conductive layer 50B (¶ 68, connector 50B) on the interposer dielectric layer top side (Fig. 6D); and
a lower signal distribution structure 46A/50A or 46A (¶ 60, a collective of under bump metallization (UBM) 46A and connector 50A, or only UBM 46A) comprising a lower signal distribution structure top side (Fig. 6D, top side of the structure 46A/50A), wherein the lower signal distribution structure top side outwardly faces the under layer bottom side (Fig. 6D) and is electrically coupled to the interposer conductive layer 36 via the under layer aperture and the interposer conductive layer bottom side (Fig. 6D).
Regarding claim 11, Chiu in Fig. 6D further teaches the interposer conductive layer bottom side is coplanar with the interposer dielectric layer bottom side (Fig. 6D, the bottom side of the lowermost layer 36 is coplanar with the bottom side of the lowermost layer 38).
Regarding claim 12, Chiu in Fig. 6D further teaches the lower signal distribution structure 46A/50A comprises a plating 46A (¶ 68, ¶ 32 disclose UBM 46A is formed by plating).
Regarding claim 13, Chu in Fig. 6D further teaches the lower signal distribution structure 46A/50A comprises a solder 50A (¶ 68, ¶ 34, connector 50A is a solder ball) coupled directly to a lower surface of the plating 46A (Fig. 6D).
Regarding claim 14, Chiu in Fig. 6D further teaches the plating 46A is laterally wider than the under layer aperture (Fig. 6D).
Regarding claim 15, Chiu in Fig. 6D further teaches the lower signal distribution structure 46A/50A comprises a lower dielectric layer 42 (¶ 29, ¶ 19, second passivation layer 42 is the same as the passivation layer 22, which is formed by dielectric material) that directly contacts the under layer bottom side (Fig. 6D, the bottom side of the layer 41).
Regarding claim 16, Chiu in Fig. 6D further teaches the under layer 41 is free of electronic devices (see Fig. 6D, no electronic devices are directly attached to the layer 41).
Regarding claim 17, Chiu in Fig. 6D further teaches an interconnection structure 50A (¶ 68, connector 50A) electrically coupled to the interposer conductive layer 36 through the lower signal distribution structure 46A (Fig. 6D, ¶ 60, ¶ 67).
Regarding claim 18, Chiu in Fig. 6D further teaches the interconnection structure 50A comprises a conductive ball or a conductive bump (¶ 34).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2008/0258300 A1 to Kobayashi et al. relates to a semiconductor device having a semiconductor chip mounted on a wiring board, and the wiring board has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
1 U.S. Patent Publication No. 2014/0252601 A1 to Lu et al. discloses in paragraph 25 that a molding compound (i.e., mold material) includes epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB).
2 U.S. Patent Publication No. 2014/0252601 A1 to Lu et al. discloses in paragraph 25 that a molding compound (i.e., mold material) includes epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB).
Prosecution Insights