Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8,11, 14-18, and 20 in the reply filed on 3/20/2026 is acknowledged.
Claims 9, 10, 12, 13, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/20/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/15/2024 and 10/16/2024 were filed after the mailing date of the Non-final rejection on 6/21/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 4/15/2024 have been approved by the examiner.
Claim Rejections - 35 USC § 112
Claims 1-8, 11, 14-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1 and 20, the phrase “ the first die has a first figure of merit (FOM) characteristic, and the second die has a second figure of merit (FOM) characteristic different from the first figure of merit (FOM) characteristic ” is vague and indefinite since it is not clear from the claim what the first figure of merit (FOM) and the second figure of merit (FOM) would be in the switching voltage regulator.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 11, and 14 insofar as being definite are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Carpenter et al. (US 9,842,797).
With respect to Claim 1, Carpenter teaches a converting circuit 300 configured to receive an input voltage and to generate an output voltage through a switching operation. A control circuit configured to cause the output voltage to be generated by controlling the switching operation. The converting circuit comprises at least one switch 315 formed on a first die 310 and configured to perform the switching
operation under control of the control circuit (i.e. the combination of 130, bonding wire 131, and 326). At least one blocking transistor (i.e. pair of lateral transistors) formed on a second die 320 and electrically connected to at least one first transistor. The first die 310 is vertically stacked on the second die 320. The first die 310 has a first figure of merit (FOM) characteristic (i.e. Low side power transistor) and the second die has a second figure of merit (FOM) characteristic (i.e. high side power transistor with lateral spaced apart transistor) different from the first figure of merit (FOM) characteristic (see col. 2 lines 19-60, col. 4 lines 10-65, and col. 5 lines 10-65; Figs. 1A, 1B, and 2-4).
With respect to Claim 2, Carpenter teaches the at least one switch formed on the first die 310 comprises a first switch configured to receive the input voltage. A second switch connected to a ground voltage, wherein the control circuit is configured to cause the first switch to open and close and to cause the second switch to open and close (see col. 4 lines 10-45)..
With respect to Claim 3, Carpenter teaches the first switch in the first die 310 comprises a plurality of p-channel metal-oxide semiconductor (PMOS) transistors connected in series. The second switch in chip 320 comprises a plurality of n-channel metal-oxide semiconductor (NMOS) transistors connected in series (see col. 3 lines 40-52 and col. 5 lines 10-20; Figs. 3 and 4).
With respect to Claim 6, Carpenter teaches the at least one blocking transistor 325, 325’ comprises a first transistor 325 electrically connected to the first switch. A second transistor 325’ connected in series to the first transistor and electrically connected to the second switch (see Figs. 3 and 4).
With respect to Claim 7, Carpenter teaches the converting circuit
further comprises at least one switch 325 or 325’ formed on the second die and configured to perform the switching operation under the control of the control circuit (see Figs. 3 and 4).
With respect to Claim 8, Carpenter teaches the at least one blocking transistor 325, 325’ comprises a p-channel metal-oxide semiconductor (PMOS) transistor electrically connected to the at least one switch formed on the first die 310. An n-channel metal-oxide semiconductor (NMOS) transistor connected in series to the
PMOS transistor and electrically connected to the at least one switch formed on the second die 320 (see col. 3 lines 39-50 and col. 2 lines 15-25).
With respect to Claim 11, Carpenter teaches the converting circuit further comprises at least one switch 325 formed on the second die and connected in series to
the at least one blocking transistor 325’ (see Figs. 3 and 4).
With respect to Claim 11, Carpenter teaches a portion of the control circuit (i.e. 326) formed on the second die 320 (see Figs. 3 and 4).
With respect to Claim 17, Carpenter teaches the first die 310 and the second die 320are bonded to each other in a face-to-face (F2F) configuration (see Figs. 3 and 4)
Allowable Subject Matter
Claim 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
11. Claims 4 are 15-18 would be allowable if rewritten or amended to overcome the
rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth
in this Office action.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of
a number of the plurality of PMOS transistors and a number of the plurality of NMOS transistors are determined based on a voltage provided to a gate of the at least one blocking transistor in claim 4.
The control circuit comprises a gate controller formed on the first die and configured to generate a first gate voltage controlling the at least one switch. A voltage generator formed on the second die and configured to generate a second gate voltage controlling the at least one blocking transistor in claim 15.
The first die and the second die are bonded to each other in a face-to-face (F2F) configuration in claim 16.
The converting circuit further comprises an inductor formed on the second die and electrically connected to the at least one blocking transistor in claim 18.
A second die stacked on the first die, wherein a plurality of transistors are formed on the second die. The blocking transistor is configured to block an input voltage. the blocking transistor and the plurality of transistors are configured to operate as a converting circuit of a DC-DC converter in claim 20,
Conclusion
12. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/June 21, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
Prosecution Insights