DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on 7/25/2026 is acknowledged.
Group II, claims 13-20 are withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-203-0164303 filed in Ministry of Intellectual Property (MOIP) on 11/23/2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 4/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanamori et al. (US 2018/0033799; hereinafter ‘Kanamori’).
Regarding claim 1, Kanamori teaches a memory device (FIGS. 3 and 6, [0018, 0021]), comprising:
a channel layer (310, FIGS. 3 and 6, [0041])
enclosing a central axis (a central longitudinal axis of the channel hole H (hereinafter ‘AX’), FIG. 3, [0041]; 310 enclosing AX) and
extending in a first direction (a first direction X, FIG. 3, [0031]; 310 extending in the first direction X, FIG. 3),
the channel layer (310) including
a side surface depressed toward the central axis (a side surface of 310 in an inter-cell region C2, FIG. 6, [0037]; hereinafter ‘310-C2’) and
a side surface protruding from the central axis (a side surface of 310 in a cell region C1, FIG. 6, [0037]; hereinafter ‘310-C1’);
a tunnel isolation layer (430, FIGS. 3 and 6, [0045])
enclosing an outer side surface of the channel layer (an outer side of 310 (hereinafter ‘310OS’); 430 enclosing 310OS, FIGS. 3 and 6, [0045]);
a charge trap layer (421, FIGS. 3 and 6, [0048])
enclosing an outer side surface of the tunnel isolation layer (an outer side surface of 430 (hereinafter ‘430OS’); 421 enclosing 430OS, FIGS. 3 and 6, [0048]);
charge trap patterns (422, FIGS. 3 and 6, [0048])
enclosing a depressed portion of the charge trap layer (annular charge trap patterns 422 extending circumferentially about the channel hole H and positioned on opposite sides of the indent portion I along the first direction X, thereby collectively enclosing the indent portion I of 421, the indent portion I including horizontal portions 421b and connection portion 421c and being indented into the inter-cell recess R, FIG. 6, [0051-0052, 0056]) and
spaced apart from each other in the first direction (422 are spaced apart from each other in the first direction X, FIG.6);
first blocking patterns (portions of 410 in C2, FIGS. 3 and 6, [0045]; hereinafter ‘410C2’) enclosing a protruding portion of the charge trap layer (410C2 enclosing a protruding portion of 421, FIG. 6);
second blocking patterns (annular portions of the cylindrical block pattern 410 in C1, FIGS. 3 and 6, [0045]; hereinafter ‘410C1’) enclosing the charge trap patterns (410C1 circumferentially surrounding 422 about the channel hole H, as shown by the cylindrical structure in FIG. 3 and the longitudinal cross-section in FIG. 6); and
gate lines (210, FIGS. 3 and 6, [0036]) enclosing the second blocking patterns (210 enclosing 410C1, FIGS. 3 and 6).
Regarding claim 2, Kanamori teaches the memory device according to claim 1, wherein:
an inner side surface of each of the charge trap patterns contacts the charge trap layer (an inner side surface of each 422 contacting 421, FIG. 6);
an outer side surface of each of the charge trap patterns contacts the second blocking patterns (an outer side surface of each 422 contacting 410C1 through 421, FIG. 6); and
a top surface and a bottom surface of each of the charge trap patterns contact the charge trap layer and the first blocking patterns (the top and bottom surfaces of each 422 contacting 421 and 410C2, FIG. 6).
Regarding claim 4, Kanamori teaches the memory device according to claim 1, wherein the charge trap layer and the charge trap patterns comprise silicon nitride layers (421 and 422 comprise silicon nitride, [0049]).
Regarding claim 6, Kanamori teaches the memory device according to claim 1, wherein the charge trap layer is a silicon oxynitride layer (421 comprises silicon oxynitride, [0049]).
Regarding claim 8, Kanamori teaches the memory device according to claim 1, wherein outer side surfaces of the charge trap patterns protrude from the depressed portion of the charge trap layer (outer side surface of 422 protruding relative to the indent portion I of 421, FIG. 6, [0052, 0056]).
Regarding claim 9, Kanamori teaches the memory device according to claim 1, wherein outer side surfaces of the second blocking patterns protrude from the first blocking patterns (outer side surface of 410C1 protrude from the depressed portion of 410C2, FIG. 6).
Regarding claim 10, Kanamori teaches the memory device according to claim 1, further comprising first material layers disposed between the gate lines and contacting side surfaces of the first blocking patterns (insulation patterns 221-226 disposed between gate line 210 and contacting side surfaces of 410C2, FIG. 6, [0034, 0037, 0045]).
Regarding claim 11, Kanamori teaches the memory device according to claim 1, wherein the tunnel isolation layer, the first blocking patterns, and the second blocking patterns comprise oxide layers (the tunnel isolation layer 430 comprises an oxide such as silicon oxide, [0062]; the first and second blocking patterns 410C2 and 410C1 comprises an oxide such as silicon oxide, hafnium oxide, or aluminum oxide, [0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kanamori (US 2018/0033799) as applied to claim 1 above, and further in view of Ueda et al. (US 2021/0257378; hereinafter ‘Ueda’).
Regarding claim 3, Kanamori teaches the memory device according to claim 1, but does not teach the memory device wherein the charge trap layer is formed of a material having a charge trap density lower than a charge trap density of the charge trap patterns.
Ueda teaches a memory device (FIG. 5H, [0012]) wherein the charge trap layer is formed of a material having a charge trap density lower than a charge trap density of the charge trap patterns (a charge trap layer 54 formed of a second charge storage material having a charge trap density lower than that of the charge trap patterns 53 formed of a first charge storage material, [0076-0078]).
As taught by Ueda, one of ordinary skill in the art would utilize and modify the above teaching into Kanamori to obtain and achieve the memory device wherein the charge trap layer is formed of a material having a charge trap density lower than a charge trap density of the charge trap patterns as claimed, because this combination allows the charge trap patterns to store more electrical charge while preventing charge diffusion from the charge trap patterns to adjacent levels, thereby providing improved programming and data retention characteristics [0079, 0133].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ueda in combination with Kanamori due to the above reason.
Regarding claim 7, Kanamori teaches the memory device according to claim 1, but does not teach the memory device wherein the charge trap layer is thinner than each of the charge trap patterns.
Ueda teaches a memory device (FIG. 5H, [0012]) wherein the charge trap layer is thinner than each of the charge trap patterns (the charge trap layer 54 has a thickness of 2-20 nm, whereas the charge trap patterns 53 has a thickness of 3-40 nm, [0074, 0078]).
As taught by Ueda, one of ordinary skill in the art would utilize and modify the above teaching into Kanamori to obtain and achieve the memory device wherein the charge trap layer is thinner than each of the charge trap patterns as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ueda in combination with Kanamori due to the above reason.
Regarding claim 12, Kanamori teaches the memory device according to claim 1, but does not teach the memory device wherein the channel layer is formed of polysilicon.
Ueda teaches a memory device (FIG. 5H, [0012]) wherein the channel layer is formed of polysilicon (channel layer 601 includes polysilicon, [0081]).
As taught by Ueda, one of ordinary skill in the art would utilize and modify the above teaching into Kanamori to obtain and achieve the memory device wherein the channel layer is formed of polysilicon as claimed, because polysilicon is suitable for conformally forming a semiconductor channel layer on a tunneling dielectric layer in a memory opening [0081].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ueda in combination with Kanamori due to the above reason.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kanamori (US 2018/0033799) as applied to claim 4 above, and further in view of Ganguly et al. (US 2011/0101442; hereinafter ‘Ganguly’).
Regarding claim 5, Kanamori teaches the memory device according to claim 1, but does not teach the memory device wherein each of the charge trap patterns has a lower nitrogen content than a nitrogen content of the charge trap layer.
Ganguly teaches a memory device (10, FIG. 3, [0045]) wherein each of the charge trap patterns has a lower nitrogen content than a nitrogen content of the charge trap layer (the charge trap pattern 34 comprises a silicon-rich silicon nitride material, while the charge trap layer 32 comprises a nitrogen-rich silicon nitride compound, [0045-0046]).
As taught by Ganguly, one of ordinary skill in the art would utilize and modify the above teaching into Kanamori to obtain and achieve the memory device wherein each of the charge trap patterns has a lower nitrogen content than a nitrogen content of the charge trap layer as claimed, because the nitrogen-rich silicon nitride provides improved charge retention, while the silicon-rich silicon nitride provides a higher charge trap density and an improved memory window [0019-0020]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ganguly in combination with Kanamori due to the above reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Yun et al. (US 2020/0091176), Lee et al. (US 2014/0061770), and KASAI et al. (US 2021/0327897) as a semiconductor device having a charge trapping structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/23/26
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