Prosecution Insights
Last updated: April 19, 2026
Application No. 18/635,792

SOLDER MOUNTING LAND AND CHARGER

Non-Final OA §102§Other
Filed
Apr 15, 2024
Examiner
DINH, TUAN T
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panasonic Automotive Systems Co. Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
916 granted / 1165 resolved
+10.6% vs TC avg
Strong +23% interview lift
Without
With
+23.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
41 currently pending
Career history
1206
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
43.4%
+3.4% vs TC avg
§102
45.0%
+5.0% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1165 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first region has a rectangular shape, claims 10 and 12” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 1 and 17 is objected to because of the following informalities: Regarding claim 1, the phrase of “A solder mounting land on which an electronic component is to be disposed via solder and the electronic component is to be mounted by soldering” is unclear because: First, there is NO the electronic component appear in any of figures. Second, as in para-0020 in the application, the applicant defined the electronic component which is one of terminal or semiconductor component, semiconductor module, capacitor, magnetic body etc. However, the electronic component is silent shows in any figures. Furthermore, as in para-0028-0036, the applicant defined the electronic component which is a lug (55) or stud (51), and the lug or stud is not the electronic component. Thus, the electronic component defined in the preamble of claim 1 have to show in the figures or remove from the claim 1. Regarding claim 17, lines 1-2, the phrase of “A solder mounting land according to the present disclosure is a land on which an electronic component is to be disposed via solder” is not understood. What does applicant mean of “according to the present disclosure”. Please, clarify. For examination, examiner suggests to change to - -A solder mounting land having a land on which an electronic component is to be via solder - - for proper reading. Regarding claim 17, line 4, please, change “the electronic component is to be mounted by soldering. The solder mounting land” to - - the electronic component is to be mounted by soldering, the solder mounting land - - for proper reading. Regarding claim 17, the phrase of “an electronic component is to be disposed via solder and the electronic component is to be mounted by soldering” is unclear because: First, there is NO the electronic component appear in any of figures. Second, as in para-0020 in the application, the applicant defined the electronic component which is one of terminal or semiconductor component, semiconductor module, capacitor, magnetic body etc. However, the electronic component is silent shows in any figures. Furthermore, as in para-0028-0036, the applicant defined the electronic component which is a lug (55) or stud (51), and the lug or stud is not the electronic component. Thus, the electronic component defined in the preamble of claim 1 have to show in the figures or remove from the claim 17. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 17 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Park (U.S. Patent 10,117,332), hereafter Park. As best understood to claim 17, Park discloses a solder mounting land (10, 20) [[according to the present disclosure is]] having a land on which an electronic component (500) is to be disposed via solder (200a, 200b) and the electronic component is to be mounted by soldering, the solder mounting land (10 or 20) as shown in figures 5A-5Ccomprising: a first region (sub-pad portion 12, 14, or 16) formed by exposing a conductive layer (120) of a substrate (110) from a solder resist layer (130) stacked on an upper surface of the conductive layer (120), the electronic component (500) being to be bonded to the first region (12, 14, 16); and a groove (the spaces or gaps formed between the sub-pad portions 12, 14, 16) formed by exposing a layer underneath the conductive layer (120), and extending from an inside to a peripheral edge portion of the first region to divide the first region (in between the sub-pad portions 12, 14, and 16). Claim(s) 1-16 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Yan et al. (U.S. 2013/0087813) submitted by the applicant, hereafter Yan. As best understood to claim 1, Yan discloses a solder mounting land (122 or 208) on which an electronic component (LED 101) is to be disposed via solder (126, para-0027) and the electronic component (101) is to be mounted by soldering, the solder mounting land as shown in figures 1-2 comprising: a first region (sub-pad portion 208 or a middle pad 122, figure 1) to which the electronic component (101) is bonded; and a second region (sub-pad portion 208 or outer pad 122, figure 1) protruding from a part of a peripheral edge portion of the first region (208) in a direction in which the first region (14) is extended in plan-view. As to claim 2, Yan further comprising a groove (210-215, para-0029) that extends from an inside to the peripheral edge portion of the first region (center of element 208, hereafter C208) to divide the first region. As to claim 3, Yan further comprising: a plurality of grooves (210-215) each extending from an inside to the peripheral edge portion of the first region (C208) to divide the first region, wherein the second region (peripheral edge 208, hereafter P208) protrudes from the peripheral edge portion of the first region (C208) between at least one pair of adjacent grooves (210, 211) among the plurality of grooves. As to claim 4, Yan discloses a groove (210) adjacent to the second region (P208) extends from the inside of the first region (C208) to a peripheral edge portion of the second region. As to claim 5, Yan discloses the first region (C208) has an annular shape that is hollow in plan view (figure 2), and each of the plurality of grooves (210-215, para-0029) radially extends from an inner edge portion to an outer edge portion of the first region. As to claim 6, Yan discloses the first region (C208) has a round shape, and each of the plurality of grooves (210-215) radially extends from a central portion to an outer edge portion of the first region. As to claims 7-8, Yan discloses the plurality of grooves (210-215) further include a groove extending concentrically in the inside of the first region, and spatially connected with a groove extending radially, para-0029. As to claim 9, Yan discloses the plurality of grooves (210-215) are formed in a lattice pattern. As to claim 10, Yan discloses the first region (C208) has a round shape or a rectangular shape, and the second region (P208) protrudes from a part of an outer edge portion of the first region. As to claim 11, Yan discloses the first region (C208) has an annular shape that is hollow in plan view, and the second region (P208) protrudes from at least one of an inner edge portion and an outer edge portion of the first region. As to claim 12, Yan discloses in figure 10 that the first region has a rectangular shape (polygonal shape), and the second region (P208) is provided at least at a part other than corner portions of the first region. As to claim 13, Yan discloses in a peripheral edge portion of the second region (P208), a peripheral edge portion opposite to the first region (C208) has a shape following a shape (round shape) of a corresponding part of the peripheral edge portion of the first region. As to claim 14, Yan discloses the second region (P208) has a shape corresponding to a size of a fillet to be formed in a peripheral edge portion of the electronic component by the solder (126). As to claim 15, Yan discloses the first region (C208) has a shape obtained by extending an outer shape of a bonding surface of the electronic component (101) by a deviation amount of an arrangement position allowed for the electronic component. As to claim 16, Yan discloses a lighting or LED device, para-0002+, having a charger (not shown) comprising: a circuit board (102) provided with the solder mounting land according to claim 1; and the electronic component (101) mounted on the circuit board (102) by soldering (126). Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Apr 15, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §102, §Other (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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APPARATUS AND METHOD FOR MANUFACTURING POWER MODULE
2y 5m to grant Granted Apr 07, 2026
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PACKAGING MODULE, ELECTRONIC DEVICE, AND METHODS FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 17, 2026
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2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+23.1%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 1165 resolved cases by this examiner. Grant probability derived from career allow rate.

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