Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-2, 4, 6-7, 10, 12, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi (PGPub No. 20230290879) in further view of Sano (US Patent No. 9985125).
Regarding claim 1, Hirabayashi teaches a semiconductor device comprising: a semiconductor part including a first main surface and a second main surface on an opposite side of the first main surface (Fig. 2 and 3 point to cross-sectional views of a semiconductor device comprising a drift layer DF (first main surface) and a substrate SB (second main surface).); a surface structure part provided on the first main surface, the surface structure part including a first electrode (Id. points to a gate wiring GW (first electrode).); a second electrode provided on the second main surface ([0050] points to a drain electrode (second electrode) that is connected to a drain region DR formed on the substrate SB (second main surface).).
Hirabayashi fails to teach a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.
Sano teaches a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part (Fig. 2 points to a protective film 126 comprising an upper horizontal portion (first protective resin film) and a lower vertical portion (second protective resin film).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that protective film(s) are formed over the upper and side surfaces of the surface structure part in order to create protective layer(s) of organic material that are unlikely to break, crack, rise, and/or peel.
Regarding claim 2, Hirabayashi in combination with Tanaka teaches wherein the second protective resin film covers a side surface of the first electrode (Figs. 2 and 3 of Hirabayashi point to the gate wiring GW (first electrode). Fig. 1 of Tanaka further points to the sealing resin 7 horizontal portions (first protective resin film)).
Regarding claim 4, Sano teaches wherein the surface structure part further includes a protective film made of oxide or nitride and provided between the first electrode and the first protective resin film and between the first electrode and the second protective resin film (Fig. 2A and Col. 12, lines 45-52 point to a protective film 125 that is made of silicon nitride.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that a protective film is formed in order to create a dense layer of inorganic material that has excellent barrier property against moisture.
Regarding claim 6, Sano teaches wherein the second protective resin film further covers a side surface of the semiconductor part (Fig. 2 points to the protective film 126. It is considered obvious that one of ordinary skill in the art would further extend the protective film 126 such that it covers both the upper surface and at least one side surface of the device (semiconductor part).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that the second protective resin film further covers a side surface of the semiconductor part in order to create a protective layer of organic material over the side surface that is unlikely to break, crack, rise, and/or peel.
Regarding claim 7, Sano teaches wherein the second protective resin film covers up to a bottom part of the side surface of the semiconductor part (Fig. 2 points to the protective film 126. It is considered obvious that one of ordinary skill in the art would further extend the protective film 126 such that it covers up to a bottom part of at least one side surface of the device (semiconductor part).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that the second protective resin film further covers up to a bottom part of the side surface of the semiconductor part in order to create a protective layer of organic material over the entire side surface that is unlikely to break, crack, rise, and/or peel.
Regarding claim 10, Sano teaches wherein the second protective resin film contains a polyimide resin, a polyamide resin, a polyolefin resin, a polybenzoxazole resin, or a silicon resin (Col. 12, lines 53-58 point the second protective film 126 being made of a polyimide resin, polybenzoxazole resin, acrylic resin, or the like.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that the second protective resin film further covers up to a bottom part of the side surface of the semiconductor part in order to create a protective layer of organic material over the entire side surface that is unlikely to break, crack, rise, and/or peel.
Regarding claim 12, Sano teaches wherein the surface structure part is not provided at an end part of the first main surface of the semiconductor part, and the second protective resin film covers the end part (Fig. 2 points to the protective film 126.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that the second protective resin film further covers an end part of the first main surface of the semiconductor part in order to create a protective layer of organic material over the entire side surface that is unlikely to break, crack, rise, and/or peel.
Regarding claim 15, Hirabayashi teaches wherein the semiconductor device is a MOSFET or an IGBT (Figs. 2 and 3 point to a main MOSFET 1MM and/or a sensing MOSFET 1SM.).
Regarding claim 16, Hirabayashi teaches wherein the first electrode is a gate wiring layer (Figs. 2 and 3 point to the gate wiring GW (first electrode).).
Claim(s) 3, 5, 8-9, 11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. in further view of Saito (PGPub No. 20230268311).
Regarding claim 3, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 5, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 8, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 9, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 11, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 13, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Regarding claim 14, Saito teaches a die pad including a first die pad main surface and a second die pad main surface on an opposite side of the first die pad main surface, wherein the second electrode is bonded to the first die pad main surface with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 with an obverse surface 101 (first die pad main surface), an electrode 201 (second electrode), and a first joining layer 21 (bonding material).); and a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film, and to expose the second die pad main surface of the die pad (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Claim(s) 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. in further view of Osugi (PGPub No. 20130264710) and Yu (PGPub No. 20210118859).
Regarding claim 17, Hirabayashi teaches a manufacturing method of a semiconductor device, the manufacturing method comprising: a semiconductor device individual piece including a semiconductor part including a first main surface and a second main surface (Fig. 2 and 3 point to cross-sectional views of a semiconductor device comprising a drift layer DF (first main surface) and a substrate SB (second main surface).), a surface structure part provided on the first main surface, the surface structure part including a first electrode (Id. points to a gate wiring GW (first electrode).), a second electrode provided on the second main surface([0050] points to a drain electrode (second electrode) that is connected to a drain region DR formed on the substrate SB (second main surface).). and a first protective resin film covering an upper surface of the surface structure part; and forming a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.
Hirabayashi fails to teach preparing a semiconductor device individual piece fixed to a dicing sheet; forming a first protective resin film covering an upper surface of the surface structure part; forming a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part; peeling off the semiconductor device individual piece from the dicing sheet; mounting the semiconductor device individual piece on a die pad with a bonding material interposed therebetween; annealing the bonding material and the second protective resin film; and forming a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film.
Sano teaches forming a first protective resin film covering an upper surface of the surface structure part; forming a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part (Fig. 2 points to a protective film 126 comprising an upper horizontal portion (first protective resin film) and a lower vertical portion (second protective resin film).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi and Sano, such that protective film(s) are formed over the upper and side surfaces of the surface structure part in order to create protective layer(s) of organic material that are unlikely to break, crack, rise, and/or peel.
Hirabayashi et al. still fails to teach preparing a semiconductor device individual piece fixed to a dicing sheet; peeling off the semiconductor device individual piece from the dicing sheet; mounting the semiconductor device individual piece on a die pad with a bonding material interposed therebetween; annealing the bonding material and the second protective resin film; and forming a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film.
Saito teaches mounting the semiconductor device individual piece on a die pad with a bonding material interposed therebetween (Fig. 12 points to an enlarged view of a semiconductor device comprising a die pad 10 and a first joining layer 21 (bonding material).); and forming a sealing part configured to bury the semiconductor part, the surface structure part, the first protective resin film, and the second protective resin film (Fig. 7 points to a sealing resin 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Saito, such that a die pad is formed in order to establish communication with external components and a sealing part if formed in order to create a layer with electric insulating properties around most of the device without compromising said communication with external components.
Hirabayashi et al. still fails to explicitly teach preparing a semiconductor device individual piece fixed to a dicing sheet; peeling off the semiconductor device individual piece from the dicing sheet; and annealing the bonding material and the second protective resin film. However, it should be noted that the processes described could be considered common practices in the art such that one of ordinary skill in the art would apply them without any explicit teachings from Hirabayashi et al.
Osugi teaches preparing a semiconductor device individual piece fixed to a dicing sheet; and peeling off the semiconductor device individual piece from the dicing sheet (Figs. 25-26 and [00169] point to a manufacturing method comprising semiconductor devices 1 mounted to a dicing sheet 31 and a UV exposure step facilitates peeling of each of the semiconductor devices 1 from the dicing sheet 31.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Osugi, such that the semiconductor device is fixed to and later peeled from a dicing sheet in order to provide a temporary carrier to improve stability during the fabrication process.
Hirabayashi et al. still fails to explicitly teach annealing the bonding material and the second protective resin film. However, it should be noted that the process(es) described could be considered common practices in the art such that one of ordinary skill in the art would apply them without any explicit teachings from Hirabayashi et al.
Saito in combination with Yu teaches annealing the bonding material and the second protective resin film (Figs. 4A-4B and [0048-49] of Yu point to a process for forming an integrated circuit package comprising the formation of die connectors 28/88, followed by a first dielectric layer 104 (second protective resin film) which can be formed before annealing. Fig. 12 of Saito further points to a semiconductor element 20 connected to a die pad 10 via a first joining layer 21 (bonding material).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Yu, such that a final structure comprising the bonding material and the second protective resin film undergoes an annealing process in order to form hybrid bonds that include both dielectric-to-dielectric bonds and metal-to-metal bonds.
Regarding claim 20, Sano teaches wherein the second protective resin film is semi-cured before the semiconductor device individual piece is peeled off from the dicing sheet (Fig. 2 points to the protective film 126. It is considered obvious that one of ordinary skill in the art would semi-cure the protective resin film prior to peeling the entire device from the dicing sheet.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Sano, such that the second protective resin film is semi-cured prior to peeling in order to optimize the balance between adhesion to the semiconductor device and release from the dicing sheet.
Claim(s) 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. in further view Kawano (PGPub No. 20180197729).
Regarding claim 18, Kawano teaches wherein the formation of the second protective resin film is performed by spraying a resin material onto the side surface of the surface structure part using an inkjet spray or an aerosol spray ([0057] points to a method of manufacturing a semiconductor device comprising the application of a high-viscosity resin (resin material) by an inkjet 40.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Kawano, such that the second protective resin film is formed using an inkjet method in order to create a passivation film of a predetermined pattern without performing patterning.
Regarding claim 19, Sano teaches wherein the second protective resin film is semi-cured before the semiconductor device individual piece is peeled off from the dicing sheet (Fig. 2 points to the protective film 126. It is considered obvious that one of ordinary skill in the art would semi-cure the protective resin film prior to peeling the entire device from the dicing sheet.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Hirabayashi et al. and Sano, such that the second protective resin film is semi-cured prior to peeling in order to optimize the balance between adhesion to the semiconductor device and release from the dicing sheet.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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