Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. In the argument submitted on 11/24/2025, Applicant argues that At pages 2 and 3 of the Office Action, the Office asserted an interpretation of Katoch in which line 260 of Katoch is considered to correspond to a recited "signal node" and circuit 410 is considered to correspond to a recited "delay stage," referring to FIG. 4 of Katoch. However, the Office did not assert an interpretation of Yang consistent with "a delay stage coupled directly connected to the signal node and configured to output a first booster signal responsive to the first control signal" as recited in claim 1 and "outputting, from a delay stage of the booster circuit, a booster signal in response to the first control signal received at the delay stage directly from the signal node" as recited in claim 17.
Applicant's arguments filed have been fully reconsidered but they are not persuasive because the delay stage can be also mapped to I1, 410 and I2 instead of only 410. Thus, the prior art Katoch teach with "a delay stage coupled directly connected to the signal node and configured to output a first booster signal responsive to the first control signal" as recited in claim 1 and "outputting, from a delay stage of the booster circuit, a booster signal in response to the first control signal received at the delay stage directly from the signal node" as recited in claim 17. In additional, a new ground of rejection of claim 1 and claim 17 are made in view of newly submitted reference Telecoo ( US 20030025532)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim(s) 1, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Telecoo ( US 20030025532)
With regard to claim 1, Telecoo teaches A circuit comprising:
a signal node ( node with sense, , Fig. 2A) configured to receive a first control signal (sense, Fig. 2A );
a delay stage ( N133, Fig. 2A)directed connected to the signal node ( sense, Fig. 2A) and configured to output a first booster signal ( bottom of N133, Fig. 2A) responsive to the first control signal( sense, Fig. 2A); and
a boost stage ( P101, N101, Fig. 2A) coupled to the signal node ( Coupled to the sense through sense) and the delay stage ( N133, Fig. 2A), wherein the boost stage comprises:
a pull-up circuit ( P101, Fig. 2A) comprising a first transistor ( P101, Fig. 2A) configured to couple the signal node (node with sense, Fig. 2A) to a power supply voltage node ( VCC, Fig. 2A) responsive to the first booster signal ( bottom node of N133 , Fig. 2A); and
a pull-down circuit ( N101, Fig. 2A) comprising a second transistor ( N101, Fig. 2A) configured to couple the signal node ( node with sense, Fig. 2A) to a reference voltage node (80, ground, Fig. 2A)responsive to the first booster signal( bottom node of N133,Fig. 2A).
With regard to claim 17, Telecoo teaches a method of operating a circuit, the method comprising:
receiving a first control signal at a signal node ( sense, Fig. 2A) of a booster circuit;
outputting, from a delay stage ( N133, Fig. 2A) of the booster circuit, a booster signal in response to the first control signal ( sense Fig. 2A); and
in response to the first control signal ( sense, Fig. 2A)and the booster signal (bottom node of N133,Fig. 2A), using a boost stage ( P102, P121, N102, N121, Fig. 2A)of the control circuit to selectively couple the signal node ( sense, Fig. 2A) to each of a power supply voltage node ( Vcc, Fig. 2A) and a reference voltage node ( GND, Fig. 2A).
With regard to claim 20, Telecoo teaches all the limitations of claim 17, and further teaches
receiving an enable signal ( Fig. 2B boost signal, at 32, 31) at the booster circuit; and
in response to the enable signal, disabling the selectively coupling the signal node to each of the power supply and reference voltage nodes ( Fig. 2B, boost signal are boost enable signal)
4. Claim(s) 1, 8. 9, 12, 14, 17-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Katoch et al. (US 12,217,792)
With regard to claim 1, Katoch et al. (US 12,217,792) teaches
A circuit comprising: a signal node (e.g., 260, Fig. 4) configured to receive a first control signal ( signal from 430, Fig. 4) ;
a delay stage ( e.g., 410& I1& I2, Fig. 4) directly connected to the signal node ( e.g., 260, Fig. 4) ( see 260 directly coupled to I1, Fig. 4) and configured to output a first booster signal ( S2, Fig. 4) responsive to the first control signal ( signal from 430, Fig. 4); and a boost stage ( e.g., 416, Fig. 4) coupled to the signal node ( e.g., 260, Fig. 4) and the delay stage( e.g., 410, I1, I2, Fig. 4), wherein the boost stage comprises: a pull-up circuit comprising a first transistor ( MP1, Fig. 4) configured to couple the signal node ( e.g., 260, Fig. 4) to a power supply voltage node (VDD, Fig. 4) responsive to the first booster signal ( S2, Fig. 4);
and a pull-down circuit ( e.g., MN1, Fig. 4)comprising a second transistor configured to couple the signal node to a reference voltage node ( GND, Fig. 4) responsive to the first booster signal ( S2, Fig. 4).
With regard to claim 8, Katoch et al. (US 12,217,792) teaches all the limitation of claim 1, and further teaches the signal node ( e.g., 260, Fig. 4) is coupled to a sense amplifier enable (SAE) distribution path ( LIO/SA) of a memory circuit ( 400, Fig. 4) and the first control signal comprises a SAE signal ( 260 is achieved through RGBLEN, which is an enable signal send to SA, SAE, Fig. 4)
With regard to claim 9, Katoch et al. (US 12,217,792) teaches a circuit comprising:
first and second signal lines (output signal line of 404, output signal of 430 Fig. 4);
a driver ( 404, 430, Fig. 4) coupled to first ends of the first and second signal lines ( output of 404, output of 430, Fig. 4) and configured to output respective first and second control signals to the first and second signal lines ( output of 404, and output of 430, Fig. 4);
a booster circuit (416, Fig. 4) coupled to a second end of the first signal line (output of 404 connected to 416, Fig. 4); and
a buffer (I1, Fig. 4) coupled between a second end of the second signal line (output of 430 connected to I1, Fig. 4) and the booster circuit (416, Fig. 4),
wherein the booster circuit (416, Fig. 4) comprises:
a delay stage (410, I2, Fig. 4) configured to output a first booster signal ( S2, Fig. 4)responsive to the first control signal (output of 404, Fig. 4) received at the second end of the first signal line(output of 430 connected to I1, Fig. 4); and
a boost stage (416, Fig. 4) coupled to the delay stage (410, I2, Fig. 4), wherein the boost stage comprises:
a pull-up circuit ( Mp1, Fig. 4)configured to couple an input terminal of the buffer ( I1, Fig. 4) to a power supply voltage node (VDD, Fig. 4) responsive to the first booster signal ( S2, Fig. 4); and
a pull-down circuit ( Mp2, Fig. 4) configured to couple the input terminal ( I1, Fig. 4) of the buffer to a reference voltage node ( GND, Fig. 4) responsive to the first booster signal ( S2, Fig. 4).
With regard to claim 12, Katoch teaches all the limitations of claim 9 and further teaches
the booster circuit ( 416, Fig. 4) is configured to cause the boost stage ( 416, Fig. 4) to couple the input terminal of the buffer ( I1, Fig. 4) to the power supply ( Vcc, Fig. 4)and reference voltage( GND, Fig. 4) nodes further responsive to an enable signal ( SAE, Fig. 4).
With regard to claim 14, Katoch teaches all the limitations of claim 9 and further teaches
the buffer comprises an inverter ( e.g., I1 is an inverter, Fig. 4).
With regard to claim 17, Katoch teaches a method of operating a circuit, the method comprising:
receiving a first control signal ( signal from 430, Fig. 4) at a signal node( e.g., 260, Fig. 4) of a booster circuit;
outputting, from a delay stage ( I1, 410 & I2 , Fig. 4) of the booster circuit ( 416, Fig. 4), a booster signal ( S2, Fig. 4) in response to the first control signal( signal from 430, Fig. 4) received at the delay stage directly from the signal node( 260, Fig. 4, I1 directly connected to 260, Fig. 4); and
in response to the first control signal ( signal from 430, Fig. 4) and the booster signal( S2, Fig. 4), using a boost stage ( MP1, MP2, MN2, MN1, Fig. 4) of the boost circuit to selectively couple the signal node to each of a power supply voltage node ( VDD, Fig. 4) and a reference voltage node (GND, Fig. 4).
With regard to claim 18, Katoch teaches all the limitations of claim 17 and further teaches
the outputting the booster signal comprises outputting a booster signal voltage ( output from 416, Fig. 4) transition delayed ( see 410 is delay, Fig. 4) from a first control signal voltage transition ( signal from 430, Fig. 4), and
the using the boost stage to selectively couple the signal node (260, Fig. 4) to each of the power supply ( VDD, Fig. 4)and reference voltage (GND, Fig. 4) nodes comprises coupling the signal node ( 260, Fig. 4) to one of the power supply or reference voltage node in response to the first control signal voltage transition ( transition of signal from 430, Fig. 4, RGBLB, which corresponding to RGBLB’ col 5, line 35-40, and Fig. 5 shows the transition from RGBLB’ from T3 to T4 cause 416 turned on during T3 and T4, MP1, MP2 turned , MN1, MN2 turned off col 13, line 15-20)and coupling the signal node ( 260, Fig. 4) to the other of the power supply or reference voltage node ( VDD or GND Fig. 4) in response to the booster signal voltage transition ( output of 416, Fig. 4).
With regard to claim 19, Katoch teaches all the limitations of claim 19. The method of claim 18, further comprising:
receiving a second control signal at the booster circuit ( see Fig. 4 RGBL’ control MP2, MN2); and
in response to a second control circuit voltage transition ( see Fig. 5, transition of RGBL’), using the boost stage to couple the signal node to the other of the power supply or reference voltage node (Fig. 5 shows the transition from RGBL’ from T3 to T4 cause 416 turned on during T3 and T4, MP1, MP2 turned , MN1, MN2 turned off col 13, line 15-20) .
Allowable Subject Matter
5 Claims 2-7, 10-11, 13, 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regard to claim 2, Katoch teaches the delay stage comprises: a first inverter ( I1, Fig. 4) comprising an input terminal coupled to the signal node ( 260, Fig. 4);
However, the prior art of record does not teach a first NAND gate comprising:
a first input terminal configured to receive an enable signal;
a second input terminal coupled to an output terminal of the first inverter; and
an output terminal configured to output the first booster signal; and
a second NAND gate comprising:
a first input terminal coupled to the output terminal of the first NAND gate;
a second input terminal configured to receive the enable signal; and
an output terminal,
the pull-up circuit further comprises a third NAND gate comprising:
a first input terminal configured to receive a second booster signal based on the first booster signal;
a second input terminal coupled to the signal node; and
an output terminal coupled to a gate of the first transistor, and
the pull-down circuit further comprises a first NOR gate comprising:
a first input terminal coupled to the output terminal of the second NAND gate;
a second input terminal coupled to the signal node; and
an output terminal coupled to a gate of the second transistor
in combination with other limitations of the claim.
Regard to claim 3-5, they depend on claim 2
Regarding to claim 6, Katoch teaches
the delay stage comprises first through third inverters coupled in series between the signal node and the boost stage ( see Fig. 6, I 1, I6, I7).
However, the prior art of record does not teach
the pull-up circuit comprises a NAND gate comprising:
a first input terminal configured to receive a first enable signal;
a second input terminal coupled to an output terminal of the third inverter;
a third input terminal configured to receive a second control signal; and
an output terminal coupled to a gate of the first transistor, and
the pull-down circuit comprises a NOR gate comprising:
a first input terminal coupled to the output terminal of the third inverter;
a second input terminal configured to receive a second enable signal;
a third input terminal coupled to the signal node; and
an output terminal coupled to a gate of the second transistor.
With regard to claim 7, Katoch teaches
the delay stage comprises first and second inverters coupled in series between the signal node and the boost stage ( see Fig. 4, I1, I2, or Fig. 6, I1 and I6).
However, the prior art of record fails to teach the boost stage comprises:
a NAND gate comprising:
a first input terminal configured to receive a first enable signal;
a second input terminal coupled to the signal node; and
an output terminal;
a NOR gate comprising:
a first input terminal coupled to the signal node;
a second input terminal configured to receive a second enable signal; and
an output terminal;
a tri-state inverter comprising:
the first and second transistors;
an input terminal coupled to an output terminal of the second inverter;
a first enable terminal coupled to the output terminal of the NAND gate;
a second enable terminal coupled to the output terminal of the NOR gate; and
an output terminal coupled to the signal node; and
one or both of:
third and fourth transistors coupled between the output terminal of the NAND gate and the power supply voltage node; or
fifth and sixth transistors coupled between the signal node and the reference voltage node.
With regard to claim 10, the prior art of record fails to teach or suggest
a third signal line coupled between the driver and the booster circuit,
wherein
the driver is configured to output a third control signal to the third signal line, and
the pull-up circuit is configured to couple the input terminal of the buffer to the power supply voltage node further responsive to the third control signal.
Claim 11 depends on claim 10.
With regard to claim 13, the prior art of record fails teach or suggest the pull-up circuit comprises a NAND gate comprising an input terminal coupled to the input terminal of the buffer; and the pull-down circuit comprises a NOR gate comprising an input terminal coupled to the input terminal of the buffer.
With regard to claim 15, the prior art of record does not teach a plurality of load circuits coupled to the second signal line between the driver and an output terminal of the buffer,
wherein each load circuit of the plurality of load circuits is configured to receive the second control signal.
Claim 16 depends on claim 15
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kulkarni (US 20160379694 A1) teaches wordline boosting technique using a self-timed capacitive charge boosting approach.
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/PINPING SUN/ Supervisory Patent Examiner, Art Unit 2872
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