Prosecution Insights
Last updated: September 15, 2026
Application No. 18/636,162

Semiconductor Device

Non-Final OA §103
Filed
Apr 15, 2024
Priority
Sep 14, 2023 — JP 2023-149525
Examiner
ESKRIDGE, CORY W
Art Unit
3624
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
464 granted / 639 resolved
+20.6% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
28 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
15.3%
-24.7% vs TC avg
§103
45.5%
+5.5% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 639 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, and 5 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ngwendson et al. (US 2022/0320323) in view of Oki et al. (US 2015/0249084). Regarding claim 1, Ngwendson teaches (FIG. 2): A semiconductor device, comprising: a first electrode (102) located in a first region, a second region, and a third region between the first region and the second region; a second electrode (130) located in the first, second, and third regions; a semiconductor part (108) located between the first electrode and the second electrode; a gate electrode (124) extending in the semiconductor part between the second electrode and the semiconductor part in the first region, the gate electrode being electrically isolated from the semiconductor part ([0091]); and a first part (232) located on the first electrode in the third region, the first part being insulative ([0094]), the semiconductor part including a first semiconductor layer (104) located on the first electrode in the first region, the first semiconductor layer being electrically connected to the first electrode, the first semiconductor layer being of a first conductivity type (p+), a second semiconductor layer (120) located on the first electrode in the second region, the second semiconductor layer being electrically connected to the first electrode, the second semiconductor layer being of a second conductivity type (n+), a third semiconductor layer (106) located on the first semiconductor layer and on the second semiconductor layer in the first and second regions, the third semiconductor layer being of the second conductivity type ([0086]), a fourth semiconductor layer (108) located on the third semiconductor layer and on the first part in the first, second, and third regions, the fourth semiconductor layer being of the second conductivity type ([0086]), a fifth semiconductor layer located on the fourth semiconductor layer (112) in the first region, the fifth semiconductor layer being electrically connected to the second electrode, the fifth semiconductor layer being of the first conductivity type (p-well), a sixth semiconductor layer (116) selectively provided on the fifth semiconductor layer, the sixth semiconductor layer being electrically connected to the second electrode, the sixth semiconductor layer being of the second conductivity type (n+), a seventh semiconductor layer (112) located on the fourth semiconductor layer in the second and third regions, the seventh semiconductor layer being electrically connected to the second electrode, the seventh semiconductor layer being of the first conductivity type (p-well), and the gate electrode (124) facing the fifth semiconductor layer via a gate insulating film ([0094]), a bottom surface of the first part contacting the first electrode, an upper surface of the first part contacting the fourth semiconductor layer, a side surface of the first part contacting the third semiconductor layer (FIG. 2). Ngwendson fails to expressly disclose an eighth semiconductor layer located on the seventh semiconductor layer and selectively provided on the fifth semiconductor layer, the eighth semiconductor layer being electrically connected to the second electrode, the eighth semiconductor layer being of the first conductivity type. However, Oki teaches anode contact regions 34a as a high concentration p-type region for improving ohmic contact with the upper electrode. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the higher concentration p-type contact region of Oki in the structure of Ngwendson for the conventional and well-known performance improvement of creating an ohmic contact with the emitter electrode. Regarding claim 2, Ngwendson teaches: The device according to claim 1, wherein the side surface of the first part contacts the fourth semiconductor layer at an upper portion of the first part (FIG. 2). Regarding claim 5, Ngwendson teaches: The device according to claim 1, wherein the third semiconductor layer is located on the first electrode, and the side surface of the first part contacts the third semiconductor layer. Regarding claim 6, Ngwendson teaches: The device according to claim 1, wherein the first part divides the third semiconductor layer in the first region and the third semiconductor layer in the second region (FIG. 2). Regarding claim 7, Ngwendson teaches trenches are formed with an oxide: The device according to claim 1, wherein the first part includes Si oxide or Si nitride. Regarding claim 8, Ngwendson teaches element 232 having two parts (FIG. 2), but fails to expressly disclose: The device according to claim 1, wherein the first part includes a void inside the first part. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the insulating structure of Ngwendson of any insulating material which is necessary or expedient, including an air gap or void, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See also Ballas Liquidating Co. v. Allied industries of Kansas, Inc. (DC Kans) 205 USPQ 331. Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ngwendson et al. (US 2022/0320323) in view of Oki et al. (US 2015/0249084) as applied to claim 1 above, and further in view of Li et al. (CN 103311287). Regarding claim 3, Ngwendson fails to expressly disclose: The device according to claim 1, further comprising: a second part on the first part in the third region, the second part having a lower carrier concentration than the fourth semiconductor layer. However, Li (FIG. 6) teaches an RC-IGBT having an oxide plug 12 on the collector, with a p- plug above for improving snapback phenomenon and softness factor (ABSTRACT). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a low concentration area above the insulating structure of Ngwendson for the predictable benefit of improving snapback performance and device softness factor. Regarding claim 4, Li teaches (FIG. 6): The device according to claim 3, wherein the second part contacts the upper surface of the first part. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
Read full office action

Prosecution Timeline

Apr 15, 2024
Application Filed
Jun 09, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
80%
With Interview (+7.2%)
2y 7m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 639 resolved cases by this examiner. Grant probability derived from career allowance rate.

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