DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (U.S. Publication No. 2024/0107763 A1; hereinafter Chung)
With respect to claim 1, Chung discloses (in Figure 6) a memory device comprising: a stacked structure located above a substrate [101] and comprising a plurality of conductive layers [130] and a plurality of insulating layers [120] arranged alternately with each other; a channel pillar [CH] passing through the stacked structure; a charge storage structure [145] (see ¶[0047]; “The channel dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the gate electrodes 130”) located between the channel pillar and the conductive layer; and a separation wall [105] passing through the stacked structure, the separation wall comprising a plurality of sub-walls stacked on each other (see Figure 6; [GS1], [GS2]), wherein of two adjacent sub-walls among the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall (see Figure 6).
With respect to claim 2, Chung discloses wherein at least one of a plurality of sidewalls of the separation wall has at least one first turn (See Figure 6).
With respect to claim 3, Chung discloses wherein each of sidewalls of the separation wall has a same number of first turns (see Figure 6).
With respect to claim 6, Chung discloses wherein the channel pillar comprises a plurality of portions stacked on each other (See Figure 6; [GS1] and [GS2]).
With respect to claim 7, Chung discloses wherein, of two adjacent portions among the plurality of portions of the channel pillar, an upper width of a lower portion is greater than a lower width of an upper portion (See Figure 6)
With respect to claim 8, Chung discloses wherein at least one of a plurality of sidewalls of the channel pillar has at least one second turn (see Figure 6).
Claim(s) 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Said et al. (U.S. Publication No. 2024/0105623 A1; hereinafter Said)
With respect to claim 12, Said discloses (in Figure 16A) a memory device comprising: a staircase structure located above a substrate [100] and comprising a plurality of conductive layers [146] and a plurality of insulating layers [132] arranged alternately with each other; a dielectric layer [165,265] covered on the staircase structure; a support pillar [20] passing through the staircase structure and the dielectric layer, wherein the support pillar comprises a plurality of sub-pillars stacked on each other (see Figure 16A; support pillars divided by wider portion in [180]), wherein of two adjacent sub-pillars among the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar (see Figure 16A).
With respect to claim 13, Said discloses wherein at least one of sidewalls of the support pillar has at least one turn (see Figure 16A).
With respect to claim 14, Said discloses wherein each of sidewalls of the support pillar has a same number of turns (see Figure 16A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Nam et al. (U.S. Publication No. 2021/0296359 A1; hereinafter Nam)
With respect to claim 4, Chung fails to disclose wherein sidewalls of the separation wall have different numbers of first turns from each other. In the same field of endeavor, Nam teaches wherein sidewalls of the separation wall have different numbers of first turns from each other (see Figure 4A). Implementation of different numbers of turns allows for the separation wall to better control the geometry where the separation wall intersections the stacked structure, thereby improving device performance (See Nam ¶[0005-0008]).Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Choi et al. (U.S. Publication No. 2024/0120007 A1; hereinafter Choi)
With respect to claim 5, Chung fails to disclose wherein the separation wall further comprises a cap part, and a width of the cap part is smaller than an upper width of the sub-wall adjacent to the cap part. In the same field of endeavor, Choi teaches wherein the separation wall [120] further comprises a cap part [155], and a width of the cap part is smaller than an upper width of the sub-wall adjacent to the cap part (See Figure 4). Implementation of a cap structure on the separation wall as taught by Choi allows for an insulating structure to be formed to better insulate the channel structures from support structures adjacent (See Choi Figure 4 and ¶[0052]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9-11 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Said
With respect to claim 9, Chung fails to disclose a support pillar that passes through a staircase structure of the stacked structure and a dielectric layer covering the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked on each other. In the same field of endeavor, Said teaches a support pillar [20] that passes through a staircase structure of the stacked structure and a dielectric layer [165,265] covering the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked on each other (see Figure 16A; support pillars divided by wider portion in [180]).
The support pillars of Said within the device of Chung improves overall structural support during processing of the device to replace sacrificial material with electrical conductive layers (see Said ¶[0164]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 10, the combination of Chung and Said discloses wherein, of two adjacent sub-pillars among the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar (See Said Figure 16A).
With respect to claim 11, the combination of Chung and Said discloses wherein at least one of a plurality of sidewalls of the support pillar has at least one third turn (see Said Figure 16A).
With respect to claim 17, Chung discloses (in Figure 6) a method of fabricating a memory device, comprising: forming a stacked structure located above a substrate [101], the stacked structure comprising a plurality of conductive layers [130] and a plurality of insulating layers [120] arranged alternately with each other; forming a channel pillar [CH] in the stacked structure; forming a charge storage structure [145] (see ¶[0047]; “The channel dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the gate electrodes 130”) between the channel pillar and the conductive layer; forming a separation wall [105] passing through the stacked structure, the separation wall comprising a plurality of sub-walls stacked on each other, wherein, of two adjacent sub-walls among the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall (see Figure 6; [GS1], [GS2]); Chung fails to disclose forming a support pillar passing through a staircase structure of the stacked structure and a dielectric layer on the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked on each other, wherein, of two adjacent sub-pillars among the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar. In the same field of endeavor, Said teaches forming a support pillar [20] passing through a staircase structure of the stacked structure and a dielectric layer [165,265] on the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked on each other (see Figure 16A; support pillars divided by wider portion in [180]), wherein, of two adjacent sub-pillars among the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar (see Figure 16A). The support pillars of Said within the device of Chung improves overall structural support during processing of the device to replace sacrificial material with electrical conductive layers (see Said ¶[0164]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, the combination of Chung and Said discloses wherein at least one of sidewalls of the separation wall has at least one first turn (see Chung Figure 6)
With respect to claim 19, the combination of Chung and Said discloses wherein at least one of sidewalls of the support pillar has at least one second turn (see Said Figure 16A)
With respect to claim 20, the combination of Chung and Said discloses wherein the at least one first turn and the at least one second turn have a same height (see Chung Figure 6)
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Said in view of Nam
With respect to claim 15, Said fails to disclose wherein sidewalls of the support pillar have different numbers of turns from each other. In the same field of endeavor, Nam teaches wherein sidewalls [SL] of a support pillar [SS] have different numbers of turns from each other (See Figure 7A).
Implementation of different numbers of turns allows for support pillars to better control the geometry where the separation wall intersections the stacked structure, thereby improving device performance and prevent collapse (See Nam ¶[0005-0008], ¶[0110]).Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Said in view of Choi
With respect to claim 16, Said fails to disclose wherein the support pillar further comprises a cap part, and a width of the cap part is smaller than an upper width of the sub-pillar adjacent to the cap part.
In the same field of endeavor, Choi teaches wherein the support pillar further comprises a cap part [182c], and a width of the cap part is smaller than an upper width of the sub-pillar adjacent to the cap part (See Figure 4). Implementation of a cap part on the support pillars of Said, as taught by Choi allows for contact structures to be formed utilizing the support structures to the staircase structure (See Choi ¶[0125]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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