DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The specification is objected because of the following reasons:
In par. [0000]: insert US Patent no. 11,996,449.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 5-7 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2017/0345903).
Re claim 1, Shimizu teaches, Figs. 1 & 4, [0024, 0048, 0079, 0088-0096, 0111, 0112, 0168], a semiconductor device comprising:
-an SiC semiconductor layer (12, 14) of a first conductivity type (n-type);
-body regions (16) of a second conductivity type (p-type) that are formed in a surface layer portion of the SiC semiconductor layer (12, 14);
-source regions (18) of the first conductivity type (n-type) that are formed in surface layer portions of the body regions (16), respectively;
-an SiO2 layer (28, 29) that covers the SiC semiconductor layer (12, 14) such as to straddle the source regions (18), and that has a first surface (of 28) in contact with the SiC semiconductor layer (12, 14) and a second surface (of 29) positioned on an opposite side to the first surface;
-a gate electrode (30) that is arranged on a part of the SiO2 layer (28, 29); and
-an upper insulating layer (32) that covers an upper portion and a side surface of the gat electrode (30);
wherein the SiO2 layer (28, 29) has:
a first region (in 28) that is formed on the first surface side and in which a carbon density gradually decreases from the first surface side to the second surface side (e.g. result from forming layer 28 on SiC drift layer 14 via thermal oxidation and first UV heat treatment [0168]); and
a second region (in 29) that is formed on the second surface side with respect to the first region (in 28), that has a carbon density lower than the carbon density of the first region (in 28), and that has a thickness of not less than a thickness of the first region (in 28) (e.g., thickness of 29 > thickness of 28).
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Shimizu does not explicitly teach a carbon density gradually decreases from not less than 1.0×1022 cm-3 to not more than 4.0×1020 cm-3.
Shimizu does teach “The carbon concentration of the silicon oxide layer 28 is, for example, equal to or greater than 2×1016 cm−3 and equal to or less than 2×1022 cm−3.” [0048] & “the carbon concentration is equal to or greater than 2×1020 cm−3 and equal to or less than 2×1021 cm−3.” [0091].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Shimizu to obtain a carbon density gradually decreases from not less than 1.0×1022 cm-3 to not more than 4.0×1020 cm-3 as claimed, because carbon density in oxide layer is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited carbon density through routine experimentation to achieve desired characteristics of the formed device. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Re claim 5, Shimizu teaches the carbon density of the carbon-density-decreasing region (of 28) gradually decreases from the carbon density of the SiC semiconductor layer (12, 14) (e.g. result from forming layer 28 on SiC drift layer 14 via thermal oxidation and first UV heat treatment) [0048, 0092, 0093, 0112].
Re claim 6, Shimizu teaches, Fig. 1, wherein the gate electrode (30) is in contact with the second region (in 29) of the SiO2 layer (28, 29).
Re claim 7, Shimizu teaches wherein the second region (in 29) has a carbon density of not more than 1.0x1019 cm-3 (e.g., less than 4×1018 cm−3) [0111-0112].
Re claim 10, Shimuzi does not explicitly teach the SiO2 layer has a breakdown electric field strength of not less than 9.0 MV.cm-1.
Shimuzi does teach the SiO2 layer (28, 29) having similar thickness and carbon concentration formed within a similar structure as the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shimuzi to arrive a breakdown electric field strength as claimed, because Shimuzi does teach similar material, similar structure and similar thickness and concentration of SiO2 layer, and with undue experimentation, one of ordinary skill in the art would easily achieve the same breakdown electric field strength as claimed.
Re claim 11, Shimuzi teaches wherein the upper insulating layer (32) includes silicon oxide [0120] or silicon nitride.
Re claim 12, Shimizu teaches wherein the SiO2 layer has a thickness of not less than 20 nm (e.g. greater than 20 nm) [0110].
Re claim 13, Shimizu teaches wherein the SiC semiconductor layer includes a SiC semiconductor substrate (12) and a SiC epitaxial layer (14) formed on the SiC semiconductor substrate (12), and the body regions (16) are formed in a surface layer portion of the SiC epitaxial layer (14) (Fig. 1).
Re claim 14, Shimizu teaches the SiC epitaxial layer (14) has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the SiC semiconductor substrate (12) [0025, 0083].
3. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu in view of Morishita (US 5,144,398).
The teachings of Shimizu have been discussed above.
Re claims 2 & 3, Shimizu does not explicitly teach the SiC semiconductor layer has a carbon density of not less than 1.0x1022 cm-3 (claim 2); and not more than 1.0x1024 cm-3 (claim 3)
Morishita teaches a concentration of C is 5x1022 cm-3 (col. 8, lines 41-42).
As taught by Morishita, one of ordinary skill in the art would utilize the above teaching to obtain a carbon density of not less than 1.0 X1022 cm-3, and not more than 1.0x1024 cm-3 as claimed, because carbon density is depended on many variable parameters such as thickness of film, crystallinity, device function, time, pressure and temperature, etc., and is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited density through routine experimentation to achieve desired characteristics of the formed device. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morishita in combination Shimizu due to above reason.
4. Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Shimizu in view of Okumura (US 2015/0028352).
The teachings of Shimizu have been discussed above.
Re claim 4, Shimizu does not teach wherein the upper insulating layer covers a portion of the second surface of the SiO2 layer that is exposed from the gate electrode.
Okumura teaches, 2A, [0077-0079], the upper insulating layer (19) covers a portion of the second surface of the SiO2 layer (17) that is exposed from the gate electrode (18).
As taught by Okumura, one of ordinary skill in the art would utilize & modify the above to obtain the upper insulating layer covers a portion of the second surface of the SiO2 layer that is exposed from the gate electrode as claimed, because it aids in enhancing gate protection and achieving device with which an increase in on-resistance can be suppressed.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Okumura in combination Shimizu due to above reason.
54. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu in view of Masuda (US 2015/0236148).
The teachings of Shimizu have been discussed above.
Re claim 8, Shimizu teaches nitrogen used in heat treatment (S111) [0093], but Shimizu does not teach a nitrogen atom density on the first surface side of the SiO2 layer is greater than a nitrogen atom density on the second surface side of the SiO2 layer.
Masuda teaches “nitrogen atoms are introduced in an interface region between gate insulating film 20 and body region 14” [0119].
As taught by Masuda, one of ordinary skill in the art would utilize and incorporate the above teaching into Shimizu to obtain a nitrogen atom density as claimed, because it aids in achieving improved channel mobility.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Masuda in combination Shimizu due to above reason.
6. Claims 15, 18, 19 and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2017/0345903) in view of Nakano et al. (US 2015/0295079).
Re claim 15, Shimizu teaches, Figs. 1 & 4, [0024, 0048, 0079, 0088-0096, 0111, 0112, 0168], a semiconductor device comprising:
-an SiC semiconductor layer (12, 14) of a first conductivity type (n-type);
-a body region (16) of a second conductivity type (p-type) that are formed in a surface layer portion of the SiC semiconductor layer (12, 14);
-source region (18) of the first conductivity type (n-type) that are formed in surface layer portions of the body region (16), respectively;
-an SiO2 layer (28, 29) that covers a part of surface of the SiC semiconductor layer (12, 14), and that has a first surface (of 28) in contact with the SiC semiconductor layer (12, 14) and a second surface (of 29) positioned on an opposite side to the first surface;
-a gate electrode (30) that is arranged on the SiO2 layer (28, 29); and
-an upper insulating layer (32) that covers the second surface of the SiO2 layer (28, 29) and the gate electrode (30);
wherein the SiO2 layer (28, 29) has:
a first surface side region (in 28) that is formed on the first surface side and in which a carbon density gradually decreases from the first surface side to the second surface side (e.g. result from forming layer 28 on SiC drift layer 14 via thermal oxidation and first UV heat treatment [0168]); and
a second surface side region (in 29) that that has a carbon density lower than the carbon density of the first surface side region (in 28), and that has a thickness of not less than a thickness of the first surface side region (in 28) (e.g., thickness of 29 > thickness of 28).
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Shimizu does not explicitly teach a carbon density gradually decreases from not less than 1.0×1022 cm-3 to not more than 4.0×1020 cm-3.
Shimizu does teach “The carbon concentration of the silicon oxide layer 28 is, for example, equal to or greater than 2×1016 cm−3 and equal to or less than 2×1022 cm−3.” [0048] & “the carbon concentration is equal to or greater than 2×1020 cm−3 and equal to or less than 2×1021 cm−3.” [0091].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Shimizu to obtain a carbon density gradually decreases from not less than 1.0×1022 cm-3 to not more than 4.0×1020 cm-3 as claimed, because carbon density in oxide layer is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited carbon density through routine experimentation to achieve desired characteristics of the formed device. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Shimizu further teach the invention may be applied to an n-channel trench MOSFET [0247], but does not explicitly teach a trench that is formed in the SiC semiconductor layer such as to penetrate the source region and the body region, the SiO2 layer covers a wall surface of the trench, and the gate electrode that is arranged in the trench via the SiO2 layer.
Nakano teaches, Fig. 7, abstract, a trench (9) that is formed in the SiC semiconductor layer (2) such as to penetrate the source region (32) and the body region (31), the SiO2 layer (gate insulating film 16) covers a wall surface of the trench (9), and the gate electrode (15) that is arranged in the trench via the SiO2 layer (16).
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As taught by Nakano, one of ordinary skill in the art would utilize/modify the above teaching to obtain a trench, the SiO2 layer and gate electrode formed in the trench as claimed, because it aids in achieving a gate trench structure with improved withstand voltage of gate insulating film.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Nakano in combination Shimizu due to above reason.
Re claim 18, Shimizu teaches the carbon density of the carbon-density-decreasing region (of 28) gradually decreases from the carbon density of the SiC semiconductor layer (12, 14) (e.g. result from forming layer 28 on SiC drift layer 14 via thermal oxidation and first UV heat treatment) [0048, 0092, 0093, 0112].
Re claim 19, Shimizu teaches, Fig. 1, wherein the gate electrode (30) is in contact with the second region (in 29) of the SiO2 layer (28, 29).
Re claim 22, Shimuzi/Nakano does not explicitly teach the SiO2 layer has a breakdown electric field strength of not less than 9.0 MV.cm-1.
Shimuzi does teach the SiO2 layer (28, 29) having similar thickness and carbon concentration formed within a similar structure as the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shimuzi to arrive a breakdown electric field strength as claimed, because Shimuzi does teach similar material, similar structure and similar thickness and concentration of SiO2 layer, and with undue experimentation, one of ordinary skill in the art would easily achieve the same breakdown electric field strength as claimed.
Re claim 23, Shimizu teaches wherein the SiO2 layer has a thickness of not less than 20 nm (e.g. greater than 20 nm) [0110].
Re claim 24, in combination cited above, Shimizu teaches the SiC semiconductor layer includes a SiC semiconductor substrate (12) and a SiC epitaxial layer (14) formed on the SiC semiconductor substrate (12), and the body regions (16) are formed in a surface layer portion of the SiC epitaxial layer (14) (Fig. 1); and Nakano teaches the trench (9) is formed in the SiC epitaxial layer (drift layer) [0055].
Re claim 25, Shimizu teaches the SiC epitaxial layer (14) has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the SiC semiconductor substrate (12) [0025, 0083].
7. Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as modified by Nakano as applied to claim 15, and further in view of Morishita (US 5,144,398).
The teachings of Shimizu/Nakano have been discussed above.
Re claims 6 & 17, Shimizu/Nakano does not explicitly teach the SiC semiconductor layer has a carbon density of not less than 1.0x1022 cm-3 (claim 16); and not more than 1.0x1024 cm-3 (claim 17)
Morishita teaches a concentration of C is 5x1022 cm-3 (col. 8, lines 41-42).
As taught by Morishita, one of ordinary skill in the art would utilize the above teaching to obtain a carbon density of not less than 1.0 X1022 cm-3, and not more than 1.0x1024 cm-3 as claimed, because carbon density is depended on many variable parameters such as thickness of film, crystallinity, device function, time, pressure and temperature, etc., and is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited density through routine experimentation to achieve desired characteristics of the formed device. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morishita in combination Shimizu/Nakano due to above reason.
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as modified by Nakano as applied to claim 15 above, and further view of Masuda (US 2015/0236148).
The teachings of Shimizu/Nakano have been discussed above.
Re claim 20, Shimizu teaches nitrogen used in heat treatment (S111) [0093], but Shimizu/Nakano does not teach a nitrogen atom density on the first surface side of the SiO2 layer is greater than a nitrogen atom density on the second surface side of the SiO2 layer.
Masuda teaches “nitrogen atoms are introduced in an interface region between gate insulating film 20 and body region 14” [0119].
As taught by Masuda, one of ordinary skill in the art would utilize and incorporate the above teaching into Shimizu to obtain a nitrogen atom density as claimed, because it aids in achieving improved channel mobility.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Masuda in combination Shimizu/Nakano due to above reason.
Double Patenting
9. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No.11,996,449. Although the claims at issue are not identical, they are not patentably distinct from each other because they both require similar claimed limitations such as SiC semiconductor layer, body regions, source regions, SiO2 layer, gate electrode, carbon density decreasing region and low carbon density region, carbon density, nitrogen atom density, trench, (gate) electrode and interfacial region, etc.
Current Application
1. A semiconductor device comprising:
an SiC semiconductor layer of a first conductivity type;
body regions of a second conductivity type that are formed in a surface layer portion of the SiC semiconductor layer;
source regions of the first conductivity type that are formed in surface layer portions of the body regions, respectively;
an SiO2 layer that covers the SiC semiconductor layer such as to straddle the source regions, and that has a first surface in contact with the SiC semiconductor layer and a second surface positioned on an opposite side to the first surface;
a gate electrode that is arranged on a part of the SiO2 layer; and
an upper insulating layer that covers an upper portion and a side surface of the gate electrode;
wherein the SiO2 layer has:
a first region that is formed on the first surface side and in which a carbon density gradually decreases from not less than 1.0×1022 cm-3 to not more than 4.0×1020 cm-3 from the first surface side to the second surface side; and
a second region that is formed on the second surface side with respect to the first region, that has a carbon density lower than the carbon density of the first region, and that has a thickness of not less than a thickness of the first region.
9. The semiconductor device according to Claim 1, further comprising:
an interfacial region that is formed in a region between the SiC semiconductor layer and the SiO2 layer, and that has an interface state density that is not more than 4.0×1011 eV-1·cm-2 in a range in which an energy level from a conduction band edge is not less than 0.2 eV and not more than 0.5 eV.
11,996,449
1. A semiconductor device comprising: an SiC semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type that are formed in a surface layer portion of the SiC semiconductor layer; a plurality of source regions of the first conductivity type that are formed in surface layer portions of the body regions, respectively; an SiO.sub.2 layer that covers the SiC semiconductor layer such as to straddle the plurality of adjacent source regions, and that has a connection surface in contact with the SiC semiconductor layer and a non-connection surface positioned on an opposite side to the connection surface; a gate electrode that is arranged on the non-connection surface of the SiO.sub.2 layer such as to expose a part of the non-connection surface; an interlayer insulating layer that covers an exposed portion of the non-connection surface of the SiO.sub.2 layer and the gate electrode; and an interfacial region that is formed in a region between the SiC semiconductor layer and the SiO.sub.2 layer, and that has an interface state density that is 4.0×1011 eV−1.cm−2 or less in a range in which an energy level from a conduction band edge is not less than 0.2 eV and not more than 0.5 eV, wherein the SiO.sub.2 layer has: a carbon-density-decreasing region that is formed in a region on the connection surface side and in which a carbon density gradually decreases from the connection surface to the non-connection surface; and a low carbon density region that is formed in a region on the non-connection surface side with respect to the carbon-density-decreasing region and that has a carbon density lower than a carbon density of the carbon-density-decreasing region.
Allowable Subject Matter
10. Claims 9 & 21 would be allowable if rewritten to overcome the rejection(s) under Double Patenting set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/2/26
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