DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-12) in the reply filed on 08/04/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 19-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (claims 19-26), there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Hideki et al (JP 2012114322A) in view of Lee et al (US20190259744A1).
Re claim 1 Hideki teaches a semiconductor chip (fig 8) [0048-0052], comprising:
an active layer (laminate film 2, fig 8) [0049] on a top surface of an underlying base substrate (1A,fig 8) [0049] said active layer (2, fig 8) [0026] having: bonding surface (TP/surface between 21 and 22 shown in fig 2c) [0026] therein that delineates an interface between a bottom active layer (21) and a top active layer (22) [0026] extending on the bottom active layer (21), and a chamfered edge (12/GV, fig 8) [0054, 0058] that extends entirely through the top active layer (see fig 8C) to fully expose a sidewall(sidewall of top 2) thereof but only partially through the bottom active layer [GV formed only in the portion of the laminated film 2 see fig 8) [0037], such that the chamfered edge (12/GV) has a vertical heigh (height of GV) [0054] less than a combined thickness of the top and bottom active layers [GV formed only in the portion of the laminated film 2] [0040];
Hideki does not teach the chamfered edge has the vertical height greater than a thickness of the top active layer and a protective layer covering at least a portion of a top surface of the active layer which extends between the protective layer and the base substrate.
Lee teaches the chamfered edge (200er, fig 12) [0057] has the vertical height (height from top to 105, fig 12) greater than a thickness (thickness of 205, fig 12) [0040] of the top active layer (205, fig 12) and a protective layer (60, fig 12) [0087-88] covering at least a portion of a top surface of the active layer (top of 205) which extends between the protective layer (60, fig 12) and the base substrate (101, fig 12) [0070].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Hideki to include the chamfered edge has the vertical height greater than a thickness of the top active layer and a protective layer covering at least a portion of a top surface of the active layer which extends between the protective layer and the base substrate as claimed.
The ordinary artisan would have been motivated to modify Hideki based on the teaching of Lee in the above manner for the purpose of enhancing process reproducibility and process stability [abstract].
Re claim 2 Hideki in view of Lee teaches the semiconductor chip of Claim 1, wherein a vertical level of a bottom of the chamfered edge (bottom of GV, fig 8c) is higher than a vertical level of the top surface of the base substrate (top of 1A, fig 8c) [Hideki, 0048].
Re claim 3 Hideki in view of Lee teaches the semiconductor chip of Claim 2, wherein, in a region where the chamfered edge (bottom portion of 2, shown in fig 8c) [Hideki0048] is not formed, a horizontal width of the active layer (left to right width of bottom 2, fig 8c) is equivalent to a horizontal width of the base substrate (left to right width of 1A) ; and
wherein, in a region (top portion of 2) [0026] where the chamfered edge (12/GV. Fig 8C) is formed, a horizontal width of the active layer (top portion of 2) decreases in a direction (vertical direction) away from the top surface of the base substrate (top of 1A, fig 8c) [0046].
Re claim 5 Hideki in view of Lee teaches the semiconductor chip of claim 1, wherein the base substrate (1A, fig 8) [Hideki 0046] further comprises a modifier (ML, fig 8c) [0047] formed along a side surface (sides of 1A, see fig 8c) [0047] of the base substrate (1A, fig 8c) [Hideki, 0047]; and
wherein the modifier (ML, fig 8c) [Hideki, 0047] is spaced apart from a bottom of the chamfered edge (12/GV) in a vertical direction (see fig 8c).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hideki et al (JP 2012114322A) modified by Lee as applied to claim 1 and further in view of Onuma et al (US20210134773A1).
Re claim 4 Hideki in view of Lee teaches the semiconductor chip of Claim 2,
Hideki and Lee do not teach a horizontal width of the top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate.
Onuma teaches a horizontal width of the top surface of the active layer is about 15 μm to about 30 μm (horizontal width 30 μm or less, fig 2) smaller than a horizontal width of a bottom surface of the base substrate (width of 18 = width of three 15 elements abt 30 μm and width two 19 groove (0.1 to 20 μm, fig 2). [0064 and 0104].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Hideki and Lee to include a horizontal width of the top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate as claimed.
The ordinary artisan would have been motivated to modify Hideki and Lee based on the teaching of Onuma in the above manner for the purpose of improving product quality of the semiconductor device [0089].
Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hideki et al (JP 2012114322A) modified by Lee as applied to claim 1 in view of Chen et al (US 11264362 B2).
Re claim 6 Hideki in view of Lee teaches the semiconductor chip of Claim 1,
Hideki and Lee do not teach the top active layer, and the bottom active layer are bonded to each other along the bonding by hybrid bonding.
Chen teaches the top active layer (104, fig 2B/2C) [col 9 lines 10-25] and the bottom active layer (204, fig 2B/2C) are bonded to each other along the bonding by hybrid bonding (col 9, lines 10-20].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chen into the structure of Hideki and Lee to include the top active layer and the bottom active layer are bonded to each other along the bonding by hybrid bonding as claimed.
The ordinary artisan would have been motivated to modify Hideki and Lee based on the teaching of Chen in the above manner for the purpose of improving the electrical characteristics of the device [0026].
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hideki et al (JP 2012114322A) in view of Lee et al (US20190259744A1) and Chen et al (US 11264362 B2).
Re claim 7 Hideki teaches a semiconductor chip, comprising:
a base substrate (1A, fig 8c) [0043];
an active layer (2, fig 8c) [0036] formed on a top surface of the base substrate (1A, fig 8c) [0043];
a first chamfer (12/GV, fig 8c) [0058] extending inside (see fig 8a) from the top surface of the active layer (2, fig 8c) and formed along an edge of the top surface of the active layer (see fig 8c);
wherein the active layer (2, fig 8c) [0026] includes a top active layer (22, shown in fig 2) [ 0026] and a bottom active layer (21, fig 8c) [0026] distinguished from each other with reference to a bonding surface (TP, top surface of 21) [0026],
Hideki does not teach a protective layer covering at least a portion of a top surface of the active layer and being apart from the base substrate in a vertical direction with the active layer therebetween;
Lee teaches a protective layer (60, fig 12) [0153] covering at least a portion of a top surface of the active layer (205/105, fig 12) [0154] and being apart from the base substrate (101, fig 12) in a vertical direction (top to bottom, fig 12) with the active layer ( 205/105, fig 12) therebetween;
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Hideki to include a protective layer covering at least a portion of a top surface of the active layer and being apart from the base substrate in a vertical direction with the active layer therebetween as claimed.
The ordinary artisan would have been motivated to modify Hideki based on the teaching of Lee in the above manner for the purpose of enhancing process reproducibility and process stability [abstract].
Hideki and Lee do not teach the bonding surface extending between the top active layer and the bottom active layer; a vertical level of a bottom of the first chamfer is lower than a vertical level of the bonding surface in the active layer.
Chen teaches the bonding surface (B1/B2, fig 2C) [col 2, line 64] extending between the top active layer (104, fig 2C) [col 3, line 22-24] and the bottom active layer (204, fig 2C) [col 6, line 32-34];
a vertical level of a bottom of the first chamfer bottom (G2, fig 3C) [col 9, line56-65] of is lower than a vertical level of the bonding surface (B1/B2, fig 3C) [col 2, line 64] in the active layer (104/204, fig 2C).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chen into the structure of Hideki and Lee to include the bonding surface extending between the top active layer and the bottom active layer; a vertical level of a bottom of the first chamfer is lower than a vertical level of the bonding surface in the active layer as claimed.
The ordinary artisan would have been motivated to modify Hideki and Lee based on the teaching of Chen in the above manner for the purpose of improving the electrical characteristics of the device [0026].
Re claim 8 Hideki in view of Lee and Chen teaches the semiconductor chip of Claim 7, wherein the vertical level of the bottom of the first chamfer (12/GV, fig 8c) [0038] is higher than a vertical level of the top surface of the base substrate (top of 1A, fig 8C) [Hideki, 0037].
Re claim 9 Hideki in view of Lee and Chen teaches the semiconductor chip of Claim 8, wherein, in a region (bottom portion of 2, shown in fig 8c) [0048] in which the first chamfer (1/GV) is not formed, a horizontal width of the active layer (left to right width of bottom 2, fig 8c) is equivalent to a horizontal width of the base substrate (left to right width of 1A); and
wherein, in a region (top portion of 2) [0026] in which the first chamfer (12/GV. Fig 8C) is formed, a horizontal width of the active layer decreases (in vertical direction) away from the base substrate (top of 1A, fig 8c) [Hideki, 0046].
Re claim 10 Hideki in view of Lee and Chen teaches the semiconductor chip of Claim 8, wherein a side surface (left side of 2, fig 8c) [0026] of the active layer (2, fig 8c) comprises a top side surface (top of 12/GV), which define the first chamfer (12/GV), and a bottom side surface (bottom of 2); and
wherein the top side surface of the active layer (top of 2, fig 8c) extends from an edge (12, fig 8c) of the top surface of the active layer (2, fig 8c) to an edge of the bottom side surface of the active layer (2, fig 8c) [Hideki, 0026].
Re claim 11 Hideki in view of Lee and Chen teaches the semiconductor chip of Claim 7, wherein the base substrate (1A, fig 8C) comprises a second chamfer (bottom of 12, fig 8C) extending inside from a top surface (fig 8a). wherein the first chamfer (12/GV, fig 8a) completely passes through the active layer (2, fig 8C); and wherein the second chamfer (bottom of 12, cut through 12) the communicates (continues) with the first chamfer (12/GV, fig 8C) [Hideki 0042].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hideki modified by Lee and Chen as applied to claims 7 and 11 and further in view of Onuma et al (US20210134773A1).
Re claim 12 Hideki in view of Lee and Chen teaches the semiconductor chip of Claim 11,
Hideki and Chen do not teach a horizontal width of a top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate; and
wherein a horizontal width of a bottom surface of the active layer is about 0.5 μm to about 15 μm smaller than the horizontal width of the bottom surface of the base substrate.
Onuma teaches a horizontal width of the top surface of the active layer is about 15 μm to about 30 μm (horizontal width is 2 μm to 15 μm in a top view, fig 2) [0034] smaller than a horizontal width of a bottom surface of the base substrate (width of 18 = width of three 15 elements abt 30 μm and width two 19 groove (0.1 to 20 μm, fig 2). [0064 and 0114]; and
wherein a horizontal width of a bottom surface of the active layer is about 0.5 μm to about 15 μm (bottom horizontal width of 15 is equal to or less than 20 μm , fig 2) [0114] smaller than the horizontal width of the bottom surface of the base substrate (width of 18 = width of three 15 elements abt 30 μm and width two 19 groove (0.1 to 20 μm, fig 2). [0064 and 0114].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Hideki, Lee and Chen to include a horizontal width of a top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate; and
wherein a horizontal width of a bottom surface of the active layer is about 0.5 μm to about 15 μm smaller than the horizontal width of the bottom surface of the base substrate as claimed.
The ordinary artisan would have been motivated to modify Hideki, Lee and Chen based on the teaching of Onuma in the above manner for the purpose of improving product quality of the semiconductor device [0089].
Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nakazawa et al US9905684B teaches semiconductor device with the semiconductor wafer diced into chips along scribe lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/29/26
