DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0123604, filed on 05/12/2024.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 04/16/2024 and 01/31/2025 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-13, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu-Xuan Huang et al, (hereinafter HUANG), US 20220359375 A1.
Regarding Claim 1, HUANG teaches a semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) comprising:
a first substrate (Figs. 27A-27B, 132, dielectric layer) which includes a first side (annotated Figure 27A) and a second side (annotated Figure 27A) that are opposite from each other in a first direction (annotated Figure 27A/27B);
a lower pattern (Figs. 27A-27B, 125, second dielectric layer) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), the lower pattern (Figs. 27A-27B, 125, second dielectric layer) extending in a second direction (annotated Figure 27A/27B) that intersects the first direction (annotated Figure 27A/27B);
a plurality of sheet patterns (Fig. 27A, 54A-54C, second nanostructures) which are spaced apart from each other in the first direction (annotated Figure 27A/27B) on the lower pattern (Figs. 27A-27B, 125, second dielectric layer);
a gate electrode (Fig. 27A, 102, gate electrodes) surrounding portions of the plurality of sheet patterns (Fig. 27A, 54A-54C, second nanostructures) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27D, 132, dielectric layer), the gate electrode (Fig. 27A, 102, gate electrodes) extending in a third direction (annotated Figure 27A/27B) that intersects the first direction (annotated Figure 27A/27B) and the second direction (annotated Figure 27A/27B);
a source/drain pattern (Figs. 27B-27D, 92, source/drain regions) which is on a first side of the gate electrode (Fig. 27C, 102, gate electrodes) and connected to the plurality of sheet patterns (Fig. 27C, 54A-54C, second nanostructures);
a power rail (Figs. 27A-27D, 134, conductive lines) which is on the second side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer) and which extends in the second direction (annotated Figure 27A/27B);
a via pattern (Figs. 27B-27D, 130, backside vias) which extends through the first substrate (Figs. 27A-27B, 132, dielectric layer) in the first direction (annotated Figure 27A/27B), the via pattern (Figs. 27B-27D, 130, backside vias) connected to the power rail (Figs. 27A-27D, 134, conductive lines) and to the source/drain pattern (Figs. 27B-27D, 92, source/drain regions);
a first dummy pattern (Figs. 27A-27D, 124, first dielectric layers) that includes an insulating material (first dielectric layers, 124 may comprises a dielectric material, [0070]) on the via pattern (Figs. 27B-27D, 130, backside vias);
a second substrate (Figs. 27A-27D, 150, carrier substrate) which includes, on the first dummy pattern (Figs. 27A-27D, 124, dielectric layers), a third side (annotated Figure 27A) that faces the first side (annotated Figure 27A), and a fourth side (annotated Figure 27A) opposite from the third side (annotated Figure 27A) in the first direction (annotated Figure 27A/27B); and
a second dummy pattern (Figs. 27A-27D, 124, dielectric layers) on the third side (annotated Figure 27A) of the second substrate (Figs. 27A-27D, 150, carrier substrate), the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) including an insulating material (first dielectric layers, 124 may comprises a dielectric material, [0070]), wherein the first dummy pattern (Figs. 27A-27D, 124, first dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, first dielectric layers) overlap each other in the first direction (annotated Figure 27A/27B).
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Regarding Claim 2, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, wherein the first dummy pattern (Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) include the same material (Fig. 28C, first dielectric layers, 124 may comprises a dielectric material, [0070]).
Regarding Claim 3, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, wherein the first dummy pattern Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) include different materials (Fig. 28C, first dielectric layers, 124 may comprises a dielectric material, [0070]) from each other.
Regarding Claim 7, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, wherein each of the first dummy pattern (Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) has at least one of a circular shape, a square shape, and a rod shape when viewed in a plan view (annotated Figure 27A, bar shape of 124 in a cross-sectional view will be the same shape in a plan view).
Regarding Claim 8, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, further comprising a source/drain contact (Figs. 27B-27D, 112, source/drain contacts) on the source/drain pattern (Figs. 27A-27D, 92, source/drain regions), wherein the via pattern (Figs. 27B-27D, 130, backside vias) is directly connected to the source/drain contact (Figs. 27B-27D, 112, source/drain contacts).
Regarding Claim 9, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, wherein the via pattern (Figs. 27B-27D, 130, backside vias) extends through the lower pattern (Figs. 27A-27B, 125, second dielectric layer) and is directly connected to the source/drain pattern (Figs. 27A-27D, 92, source/drain regions).
Regarding Claim 10, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1, further comprising:
a field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), the field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) covering a side wall (annotated Figure 27A) of the lower pattern (Figs. 27A-27B, 125, second dielectric layer); and
a source/drain contact (Figs. 27B-27D, 112, source/drain contacts) on the source/drain pattern (Figs. 27A-27D, 92, source/drain regions), wherein the via pattern (Figs. 27B-27D, 130, backside vias) extends through the field insulation film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material), and wherein an upper side (annotated Figure 27A) of the via pattern (Figs. 27B-27D, 130, backside vias) is coplanar (Fig. 27D, the backside vias, 130, may be similar to the source/drain contacts, 112, [0083]) with an upper side (annotated Figure 27A) of the source/drain contact (Figs. 27B-27D, 112, source/drain contacts).
Regarding Claim 11, HUANG teaches a semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) comprising:
a first substrate (Figs. 27A-27B, 132, dielectric layer) including a first side (annotated Figure 27A) and a second side (annotated Figure 27A) that are opposite to each other in a first direction (annotated Figure 27A/27B);
a lower pattern (Figs. 27A-27B, 125, second dielectric layer) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), the lower pattern (Figs. 27A-27B, 125, second dielectric layer) extending in a second direction (annotated Figure 27A/27B) that intersects the first direction (annotated Figure 27A/27B);
a field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer) and on a side wall (annotated Figure 27A) of the lower pattern (Figs. 27A-27B, 125, second dielectric layer);
a plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures) which are spaced apart from each other in the first direction (annotated Figure 27A/27B) on the lower pattern (Figs. 27A-27B, 125, second dielectric layer);
a gate electrode (Figs. 27A, 27C-27D, 102, gate electrodes) surrounding portions of the plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), the gate electrode (Figs. 27A, 27C-27D, 102, gate electrodes) extending in a third direction (annotated Figure 27A/27B);
a source/drain pattern (Figs. 27A-27D, 92, source/drain regions) which is on one side of the gate electrode (Figs. 27A, 27C-27D, 102, gate electrodes) and connected to the plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures);
a power rail (Figs. 27A-27D, 134, conductive lines) on the second side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer) and extending in the second direction (annotated Figure 27A/27B);
a via pattern (Figs. 27B-27D, 130, backside vias) which extends through the first substrate (Figs. 27A-27B, 132, dielectric layer) and the field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) in the first direction (annotated Figure 27A/27B), and is connected to each of the power rail (Figs. 27A-27D, 134, conductive lines) and the source/drain pattern (Figs. 27A-27D, 92, source/drain regions);
a first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer);
a first dummy pattern (Figs. 27A-27D, 124, dielectric layers) arranged in the first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]), the first dummy pattern (Figs. 27A-27D, 124, dielectric layers) including an insulating material that is a different material than a material included in the first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]);
a second substrate (Figs. 27A-27D, 150, carrier substrate) which includes, on the first dummy pattern (Figs. 27A-27D, 124, dielectric layers), a third side (annotated Figure 27A) that faces the first side (annotated Figure 27A), and a fourth side (annotated Figure 27A) that is opposite to the third side (annotated Figure 27A) in the first direction (annotated Figure 27A/27B);
a second insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) on the third side (annotated Figure 27A) of the second substrate (Figs. 27A-27D, 150, carrier substrate); and
a second dummy pattern (Figs. 27A-27D, 124, dielectric layers) in the second insulating film and including an insulating material that is different from a material included in the second insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]), wherein the first dummy pattern (Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) are offset in the first direction (annotated Figure 27A/27B).
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Regarding Claim 12, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11, wherein the first dummy pattern (Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) include the same material (Fig. 28C, first dielectric layers, 124 may comprises a dielectric material, [0070]).
Regarding Claim 13, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11, wherein the first dummy pattern Figs. 27A-27D, 124, dielectric layers) and the second dummy pattern (Figs. 27A-27D, 124, dielectric layers) include different materials (Fig. 28C, first dielectric layers, 124 may comprises a dielectric material, [0070]) from each other.
Regarding Claim 18, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11, wherein the first insulating film and the second insulating film include the same material (first dielectric layers, 124 may comprises a dielectric material, [0070]).
Regarding Claim 19, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11, wherein the first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) includes the same material as the second dummy pattern (Figs. 27A-27D, 124, dielectric layers), and wherein the second insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) includes the same material as the first dummy pattern (Figs. 27A-27D, 124, dielectric layers).
Regarding Claim 20, HUANG teaches a semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) comprising:
a first substrate (Figs. 27A-27B, 132, dielectric layer) which includes a first side (annotated Figure 27A) and a second side (annotated Figure 27A) that are opposite from each other in a first direction (annotated Figure 27A/27B);
a plurality of lower patterns (Figs. 27A-27B, 125, second dielectric layer) which extend in a second direction (annotated Figure 27A/27B) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), and are spaced apart from each other in a third direction (annotated Figure 27A/27B);
a field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) on side walls (annotated Figure 27A) of the plurality of lower patterns (Figs. 27A-27B, 125, second dielectric layer), on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer);
a plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures) which are spaced apart from each other in the first direction (annotated Figure 27A/27B), on the plurality of lower patterns (Figs. 27A-27B, 125, second dielectric layer);
a plurality of gate electrodes (Figs. 27A, 27C-27D, 102, gate electrodes) which surround portions of the plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer), extend in the third direction (annotated Figure 27A/27B), and are spaced apart from each other in the second direction (annotated Figure 27A/27B);
a plurality of source/drain patterns (Figs. 27A-27D, 92, source/drain regions) which are between the plurality of gate electrodes (Figs. 27A, 27C-27D, 102, gate electrodes), each of the plurality of source/drain patterns (Figs. 27A-27D, 92, source/drain regions) connected to at least one of the plurality of sheet patterns (Figs. 27A-27D, 54A-54C, second nanostructures);
a plurality of source/drain contacts (Figs. 27B-27D, 112, source/drain contacts) which are on each of the plurality of source/drain patterns (Figs. 27A-27D, 92, source/drain regions);
a power rail (Figs. 27A-27D, 134, conductive lines) which is on the second side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer) and which extends in the second direction (annotated Figure 27A/27B);
a plurality of via patterns (Figs. 27B-27D, 130, backside vias) which extend through the first substrate (Figs. 27A-27B, 132, dielectric layer) and the field insulating film (Figs. 27A-27D, 125, second dielectric layer includes a metal oxide material) in the first direction (annotated Figure 27A/27B), and are connected to each of the power rail (Figs. 27A-27D, 134, conductive lines) and the plurality of source/drain patterns (Figs. 27B-27D, 112, source/drain contacts);
a first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) on the first side (annotated Figure 27A) of the first substrate (Figs. 27A-27B, 132, dielectric layer);
a first dummy pattern (Figs. 27A-27D, 124, dielectric layers) which extends through the first insulating film, and includes an insulating material that is different from a material included in the first insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]);
a first adhesive film (Figs. 27A-27D, optional adhesion layer may be deposited, [0072]) which covers the first insulating film and the first dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]);
a second substrate (Figs. 27A-27D, 150, carrier substrate) which includes, on the first dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]), a third side (annotated Figure 27A) that faces the first side (annotated Figure 27A), and a fourth side (annotated Figure 27A) opposite to the third side (annotated Figure 27A) in the first direction (annotated Figure 27A/27B);
a second insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]) on the third side (annotated Figure 27A) of the second substrate (Figs. 27A-27D, 150, carrier substrate);
a second dummy pattern (Figs. 27A-27D, 124, dielectric layers) which extends through the second insulating film, and includes an insulating material that is a different material from a material included in the second insulating film (first dielectric layers, 124 may comprises a dielectric material, [0070]); and
a second adhesive film (Figs. 27A-27D, optional adhesion layer may be deposited, [0072]) which covers the second insulating film and the second dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]),
wherein the first adhesive film is bonded to the second adhesive film (Figs. 27A-27D, optional adhesion layer may be deposited, [0072]),
wherein each of the first dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]) and the second dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]) has at least one of a circular shape, a quadrangular shape, and a bar shape when viewed in a plan view (annotated Figure 27A, bar shape of 124 in a cross-sectional view will be the same shape in a plan view),
wherein the first dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]) and the second dummy pattern (first dielectric layers, 124 may comprises a dielectric material, [0070]) overlap each other in the first direction (annotated Figure 27A/27B),
wherein the first insulating film and the second insulating film include the same material (first dielectric layers, 124 may comprises a dielectric material, [0070]), and
wherein the first dummy pattern and the second dummy pattern include the same material (first dielectric layers, 124 may comprises a dielectric material, [0070]).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG as applied to Claim(s) 1-2, 7-13, and 18-20, in view of Jeffrey Smith et al, (hereinafter SMITH), US 20210028169 A1..
Regarding Claim 4, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 1.
HUANG does not explicitly disclose the semiconductor device, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and wherein a depth of the first sub-pattern in the first direction is different from a depth of the second sub-pattern in the first direction.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein the first dummy pattern (annotated Figure 21) includes a first sub-pattern (annotated Figure 21, 2120, patterns) and a second sub-pattern (annotated Figure 21, 2120, patterns), and
wherein a depth (annotated Figure 21, D1) of the first sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is different from a depth (annotated Figure 21, D2) of the second sub-pattern (annotated Figure 21, 2120, patterns)in the first direction (annotated Figure 21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of SMITH, such that the semiconductor device, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and wherein a depth of the first sub-pattern in the first direction is different from a depth of the second sub-pattern in the first direction, so that the patterns, 1230, the trenches, 1330, the patterns, 1620, and the trenches, 1720 can be modified to form the stack of FETs (SMITH, [0139]).
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Regarding Claim 5, HUANG as modified by SMITH teaches the semiconductor device of claim 4.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein the second dummy pattern (annotated Figure 21) includes a third sub-pattern (annotated Figure 21, 2120, patterns) and a fourth sub-pattern (annotated Figure 21, 2120, patterns), and wherein a depth (annotated Figure 21, D3) of the third sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is different from a depth (annotated Figure 21, D4) of the fourth sub-pattern in the first direction (annotated Figure 21, 2120, patterns).
Regarding Claim 6, HUANG as modified by SMITH teaches the semiconductor device of claim 5.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein the depth (annotated Figure 21, D1) of the first sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D1 < D2) than the depth (annotated Figure 21, D2) of the second sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21),
wherein the depth (annotated Figure 21, D3) of the third sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D3 < D4) than the depth (annotated Figure 21, D2) of the fourth sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21),
wherein the first sub-pattern (annotated Figure 21, 2120, patterns) and the third sub-pattern (annotated Figure 21, 2120, patterns) and overlap (annotated Figure 21, 2120, patterns) and in the first direction (annotated Figure 21), and
wherein the second sub-pattern (annotated Figure 21, 2120, patterns) and the fourth sub-pattern (annotated Figure 21, 2120, patterns) overlap (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21).
Regarding Claim 14, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11.
HUANG does not explicitly disclose the semiconductor device, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and wherein a depth of the first sub-pattern in the first direction is smaller from a depth of the second sub-pattern in the first direction.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein the first dummy pattern (annotated Figure 21) includes a first sub-pattern (annotated Figure 21, 2120, patterns) and a second sub-pattern (annotated Figure 21, 2120, patterns), and
wherein a depth (annotated Figure 21, D1) of the first sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D1 < D2) from a depth (annotated Figure 21, D2) of the second sub-pattern (annotated Figure 21, 2120, patterns)in the first direction (annotated Figure 21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of SMITH, such that the semiconductor device, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and wherein a depth of the first sub-pattern in the first direction is different from a depth of the second sub-pattern in the first direction, so that the patterns, 1230, the trenches, 1330, the patterns, 1620, and the trenches, 1720 can be modified to form the stack of FETs (SMITH, [0139]).
Regarding Claim 15, HUANG as modified by SMITH teaches the semiconductor device of claim 14.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein the second dummy pattern (annotated Figure 21) includes a third sub-pattern (annotated Figure 21, 2120, patterns) and a fourth sub-pattern (annotated Figure 21, 2120, patterns), and wherein a depth (annotated Figure 21, D3) of the third sub-pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D3 < D4) from a depth (annotated Figure 21, D4) of the fourth sub-pattern in the first direction (annotated Figure 21, 2120, patterns).
Regarding Claim 16, HUANG teaches the semiconductor device (Fig. 1, nano-FETs in a three-dimensional view, [0012]) of claim 11.
HUANG does not explicitly disclose the semiconductor device, the semiconductor device, wherein a depth of the first dummy pattern in the first direction is smaller than a height of the first insulating film in the first direction.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein a depth (annotated Figure 21, D1) of the first dummy pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D1 < DF) than a height (annotated Figure 21, H1) of the first insulating film (Fig. 21, 2010, patterning material) in the first direction (annotated Figure 21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of SMITH, such that the semiconductor device, wherein a depth of the first dummy pattern in the first direction is smaller than a height of the first insulating film in the first direction, so that the one or more patterning materials, 1210, such as SoC, are formed, wherein the patterns, 1230, are generated in the gate cut structure of the semiconductor apparatus, 400 (SMITH, [0114]).
Regarding Claim 17, HUANG as modified by SMITH teaches the semiconductor device of claim 16.
SMITH teaches the semiconductor device (Fig. 21, 400, semiconductor apparatus), wherein a depth (annotated Figure 21, D2) of the second dummy pattern (annotated Figure 21, 2120, patterns) in the first direction (annotated Figure 21) is smaller (annotated Figure 21, D1 < H1) than a height (annotated Figure 21, H1) of the first insulating film (Fig. 21, 2010, patterning material) in the first direction (annotated Figure 21).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220230947 A1 – Figures 8A-8E
STATEMENT OF RELEVANCE – Method of manufacturing a backside power distribution network (BSPDN) semiconductor architecture.
US 20230178433 A1 – Figures 14
STATEMENT OF RELEVANCE – Cross-sectional view of the semiconductor structure, where the first buried power rail (BPR) is completely removed.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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