DETAILED ACTION
This correspondence is in response to the communications received April 16, 2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The following is an analysis of parent Application claims against the instant application.
1.) 17/193,594 now US 11,723,194, which is not applicable, as all claims are directed to structures.
2.) 17/818,954, now US 11,963,348, which consists of method claims that appear to read on the instant application’s claim set.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 and 18-20 of U.S. Patent No. 11,963,348. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations.
It is noted here, that the repetition of the claim language in the following rejections will be included only when it is not readily apparent how the claims share similar limitations or when obviousness type rejection is required. When claim numbers are only stated, it should be readily apparent to the reader, which limitations are shared by the instant application and the parent application.
Claim limitation(s) of the instant application
Claim limitation(s) of the ‘348 patent
1. A method of making an integrated circuit, comprising:
A. forming a transistor in an active area by forming a A1. gate electrode over the active area; [it is noted that the terms “active area” and “channel” are analogous]
forming a source region and a drain region on opposite sides of the gate electrode with a channel region under the gate electrode;
B. removing a portion of the gate electrode and an underlying portion of the channel to form a first trench that separates a first portion of the active area and a second portion of the active area;
C. depositing a dielectric material to fill the first trench and form a first trench isolation structure between the first portion of the active area and the second portion of the active area;
D. forming a plurality of contacts comprising a gate electrode contact, a source region contact, and a drain region contact; and
E. forming a power rail electrically E1. connected to the source region contact;
F. forming a bit line F1. electrically connected to the drain region contact; and
G. forming a word line G1. electrically connected to the gate electrode contact.
1. A method of making an integrated circuit read only memory (ROM) structure, comprising:
A. forming a ROM transistor by implanting an active area in a substrate to define a channel, a source region, and a drain region;
A1. depositing a gate electrode over the channel;
B. removing a portion of the gate electrode and an underlying portion of the channel to form a trench separating a first portion of the active area and a second portion of the active area;
C. depositing a dielectric material to fill the trench and form a trench isolation structure to isolate the first portion of the active area from the second portion of the active area;
depositing a conductive line over at least one of the source region and the drain region;
adding dopants to the source region and the drain region of the active area;
D. forming a plurality of contacts comprising a gate electrode contact, a source region contact, and a drain region contact; and
E. depositing a power rail, F. a bit line, and at least one G. word line of the integrated circuit over the contacts.
E1. is satisfied by claim 6’s portion, “a gate electrode tie-off contact configured to electrically connect the gate electrode to a power rail”.
F1. is satisfied by claim 7’s, “etching a second opening through the ILD to expose a first drain contact;
…
filling the second opening to form a bit line;”.
G1. is satisfied by claim 7’s, “etching a third opening through the ILD to expose a gate electrode contact;
…
filling the third opening to form a word line.”
2. The method of claim 1, wherein removing a portion of the gate electrode and an underlying portion of the channel further comprises:
forming an etch pattern over the gate electrode, wherein a first opening in the etch pattern exposes a first portion of the gate electrode; and
etching the first portion of the gate electrode and an underlying first portion of the channel.
Claim 2.
3. The method of claim 2, further comprising: etching the underlying first portion of the channel for a period sufficient to remove the first portion of the channel and expose an underlying material.
4. The method of claim 2, further comprising: forming a second opening in the etch pattern to expose a second portion of the gate electrode; and etching the second portion of the gate electrode and an underlying second portion of the channel to form a second trench.
Claim 3. Which essentially states that at the patterned region opening, the etch removes the exposed portion of the gate and channel, and the etch is carried out until the opening exposes the top surface of the substrate. Where the removed gate portion is the first trench and the removed channel portion is the second trench.
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
5. The method of claim 1, further comprising: forming a gate electrode tie-off contact configured to electrically connect the gate electrode to the power rail.
Claim 6.
6. The method of claim 1, further comprising:
depositing an inter-layer dielectric (ILD) over the gate electrode, the source region, and the drain region, wherein the plurality of contacts comprise a first source region contact, a first drain region contact, and a first gate electrode contact through the ILD;
connecting the first source region contact to the power rail;
connecting the first drain region contact to the bit line; and
connecting the first gate electrode contact to the word line.
Claim 7.
7. The method of claim 6, further comprising:
forming a second source region contact; and
electrically connecting the first source region contact to the second source region contact.
Claim 8.
8. The method of claim 4, further comprising:
depositing the dielectric material to fill the second trench and form a second trench isolation structure between a third portion of the active area and a fourth portion of the active area.
Claim 5.
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
9. The method of claim 4, further comprising etching the underlying first portion of the channel for a period sufficient to remove the first portion of the channel and expose a first portion of an underlying material in the first trench; etching the underlying second portion of the channel for a period sufficient to remove the second portion of the channel and expose a second portion of the underlying material in the second trench; and filling the first trench and the second trench with the dielectric material.
Claim 3. Which essentially states that at the patterned region opening, the etch removes the exposed portion of the gate and channel, and the etch is carried out until the opening exposes the top surface of the substrate. Where the removed gate portion is the first trench and the removed channel portion is the second trench.
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
10. A method of manufacturing a ROM circuit structure, comprising:
A. forming a first transistor comprising a first source, a first source conductive line in electrical contact with the first source, a first drain, a first gate electrode, and a first drain conductive line in electrical contact with the first drain;
B. forming a second transistor comprising a second gate electrode, a second channel, a second drain, the first source, and a second drain conductive line over the second drain;
C. removing a portion of the second gate electrode and an underlying portion of the second channel to form a trench separating the first source and the second drain;
D. depositing a dielectric material to fill the trench and isolate the first source and the second drain; and
E. forming a bit line that electrically connects the first drain conductive line to the second drain conductive line.
10. A method of manufacturing an integrated circuit structure, comprising:
A. forming a first transistor comprising a first gate electrode, a first channel, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
B. forming a second transistor comprising a second gate electrode, a second channel, a second drain, the first source, and a second drain conductive line over the second drain;
C. removing a portion of the second gate electrode and an underlying portion of the second channel to form a trench separating the first source and the second drain;
D. depositing a dielectric material to fill the trench and isolate the first source and the second drain; and
E. forming a bit line that electrically connects the first drain conductive line to the second drain conductive line.
11. The method according to claim 10, further comprising:
positioning the first gate electrode relative to the second gate electrode whereby the first gate electrode and the second gate electrode are separated by a conductive line separation interval.
Claim 11.
12. The method according to claim 10, further comprising:
positioning the first gate electrode relative to the second gate electrode whereby the first gate electrode and the second gate electrode are separated by two conductive line separation intervals.
Claim 12.
13. The method according to claim 10, further comprising: forming a power rail; and electrically connecting the first source conductive line and a second source conductive line to the power rail.
Claim 13.
14. The method according to claim 10, further comprising: forming a third gate electrode, forming a second source on a first side of the third gate electrode; forming a second source conductive line electrically connected to the first source conductive line; forming a third drain on a second side of the third gate electrode opposite the second source; and forming a third drain conductive line.
Claim 14.
15. The method according to claim 14, further comprising: forming a third transistor with the third drain, the third gate electrode, and the second drain; and connecting the second drain of the second transistor to the third drain to provide a bit value for the third transistor.
Claim 15.
16. A method of manufacturing an integrated circuit structure, comprising:
A. forming a first transistor comprising a first gate electrode, a A1. first gate electrode contact, a first source, a A2. first source contact, a first drain, and a A3. first drain contact;
A3. forming a drain conductive line electrically connected to the first drain contact [this “first drain contact” is the interface at which the ‘348 patent’s “first drain” makes electrical connection with “drain conductive line”];
A2. forming a first source conductive line electrically connected to the first source contact;
B. forming a power rail electrically connected to the first source contact and a first gate electrode tie-off contact,
C. wherein the first gate electrode tie-off contact electrically connects the power rail to the first gate electrode; and
D. forming a second transistor comprising a second gate electrode, a second gate electrode contact, a second source, a second source contact, a second drain, and a second drain contact; and [this “second drain contact” is the interface at which the ‘348 patent’s “second drain” makes electrical connection with “drain conductive line”]
E. forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.
16. A method of manufacturing an integrated circuit structure, comprising:
A3. forming a first drain contact;
forming a drain conductive line electrically connected to the first drain contact;
A. forming a first transistor comprising:
forming a first gate electrode, A1. forming a first gate electrode contact, forming a first source, forming a first source conductive line electrically connected to the first source, forming a A2. first source contact electrically connected to the first source conductive line, forming a first drain A3. electrically connected to the drain conductive line, and
B. forming a power rail electrically connected to the first source contact and a first gate electrode tie-off contact,
C. wherein the first gate electrode tie-off contact electrically connects the power rail to the first gate electrode; and
D. forming a second transistor comprising forming a second gate electrode, forming a second gate electrode contact connected to the second gate electrode, forming a second source, forming a second source conductive line connected to the second source, forming a second source contact connected to the second source conductive line and the power rail;
D. forming a second drain electrically connected to the drain conductive line; and
E. forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.
17. The method according to claim 16, further comprising:
forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.
This limitation is satisfied by claim 16’s limitation of, “E. forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.”
18. The method according to claim 16, further comprising: positioning the first gate electrode relative to a second gate electrode to provide a gate electrode separation interval; and positioning the first source conductive line relative to a second source conductive line to provide a conductive line separation interval.
Claim 18.
19. The method according to claim 16, further comprising: forming a bit line electrically connected to the first drain contact.
Claim 19.
20. The method according to claim 19, further comprising:
forming a third transistor comprising:
forming a third gate electrode, forming a third gate electrode contact, forming a third drain, forming a second drain conductive line, and forming a second drain contact;
electrically connecting the second drain contact to the bit line;
positioning the third gate electrode relative to the first gate electrode to provide a first separation distance of one gate electrode separation interval; and
positioning the second gate electrode relative to the third gate electrode to provide a second separation distance of two gate electrode separation intervals.
Claim 20.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893