Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on May 9, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 16, 2024, December 16, 2024 is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Device Embodiment 1 (Figs. 8 and 11) in the reply filed on August 19, 2026 is acknowledged. The traversal is on the ground(s) that the dummy pattern distinction of the embodiments does not impose a serious search and examination burden. This is found persuasive and previous restriction requirement of July 16, 2026 is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 and 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “a frontside contact” in both lines 4 and 5. It is unclear if each instance of “a frontside contact” is a new frontside contact or if it is meant to refer to the original instance of frontside contact defined in claim 1. For purposes of examination this will be interpreted as “ the frontside contact between the bit line and the third source/drain region; and the frontside contact between the bit line and the fourth source/drain region.”
Claim 9 recites the limitation “a backside contact” in both lines 4 and 5. It is unclear if each instance of “a backside contact” is a new backside contact or if it is meant to refer to the original instance of backside contact defined in claim 1. For purposes of examination this will be interpreted as “the backside contact between the power line and the third source/drain region; and the backside contact between the power line and the fourth source/drain region.” Claim 21 recites the limitation “a frontside contact” in both lines 4 and 5. It is unclear if each instance of “a frontside contact” is a new frontside contact or if it is meant to refer to the original instance of frontside contact defined in claim 19. For purposes of examination this will be interpreted as “ the frontside contact between the bit line and the third source/drain region; and the frontside contact between the bit line and the fourth source/drain region.”
Claim 22 recites the limitation “a backside contact” in both lines 4 and 5. It is unclear if each instance of “a backside contact” is a new backside contact or if it is meant to refer to the original instance of backside contact defined in claim 19. For purposes of examination this will be interpreted as “the backside contact between the power line and the third source/drain region; and the backside contact between the power line and the fourth source/drain region.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 19-20, and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng (US 2021/0391318).
Claim 1, Peng discloses (Figs. 2A-2B and 16) an integrated circuit comprising a read only memory (ROM) cell which comprises an on-cell (Fig. 16 shows circuit can be used in read only memory, Para [0080]) , wherein the on-cell comprises: a first source/drain region (262B, source/drain region, Para [0045]) and a second source/drain region (262A, source/drain region, Para [0045]); a frontside contact (265B/275, metal diffusion/via contact, Para [0045], hereinafter “front”) between the first source/drain region (frontis between 262B and 270) and a bit line (270, front side metal rail which electrical signals can be provided, Para [0046]) on a front side of the on-cell (270 is on the front side of the circuit, Par a[0045]); and a backside contact (240A/VDB/250A, backside metal rails/contact layer/via contact, Para [0042],[0046], hereinafter “back”) between (back is between 262A and 210A) the second source/drain region (262A) and a power line (210A, backside power rails, Para [0042]) on a back side of the on-cell (210A are in the backside of the integrated circuit, Para [0042]), wherein the bit line is configured to provide a bit line signal to the on-cell (since 270 allows for electrical signals to be provided it will provide bit signal, Para [0046]), wherein the power line is configured to provide a power supply voltage signal to the on-cell (210A provides backside power, Para [0042]), and wherein the bit line and the power line are vertically aligned with each other (270 and 210A are vertically aligned). Claim 2, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 1, wherein the on-cell further comprises a gate line (220A-220C, gate regions, Para [0045]), extending in a first horizontal direction (220A-220C extend in X-direction for example).
Claim 3, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 2, wherein the bit line (270) and the power line (210A) are extended in a second horizontal direction perpendicular to the first horizontal direction (as can be seen in Fig. 2A, 210A extends in Y-direction and M0 which is also 270 extends in Y-direction which is perpendicular to X-direction). Claim 4, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 3, wherein the bit line and the power line pass through a center of the on-cell (under BRI Fig. 2B shows 270 and 210A would pass through a center vertical line drawn in the Z-direction). Claim 5, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 1, wherein the frontside contact (front) comprises: an active contact (265B, metal diffusion, Para [0045]) on the first source/drain region (265B is on 262B); and an active via (275, via contact, Para [0045]) between the active contact and the bit line (275 is between 265B and 270). Claim 6, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 1, wherein the backside contact (back) comprises an active via (250A, via contact, Para [0042]) on the second source/drain region and the power line (250A is on the bottom surface of 262A and on the top surface of 210A). Claim 7, Peng discloses (Figs. 2A-2B and 16) the integrated circuit of claim 1, wherein the backside contact (back) comprises: an active contact (VDB, contact layer, Para [0042]) on the second source/drain region (VDB is on the bottom surface of 262A); and an active via (250A, via contacts, Para [0042]) between the active contact and the power line (250A is between VDB and 210A). Claim 19, Peng discloses (See annotated Figs. 2A-2B and Fig. 16) an integrated circuit comprising a read only memory (ROM) cell comprising an on-cell (Fig. 16 shows circuit can be used in read only memory, Para [0080]) which comprises: a first source/drain region (262B, source/drain region, Para [0045]) and a second source/drain region (262A, source/drain region, Para [0045]); a backside contact (265B/275, metal diffusion/via contact, Para [0045], hereinafter “back”) between (back is between 270 and 262B) a bit line (270, metal rail which electrical signals can be provided, Para [0046]) in a backside metal layer (270 is in M0) on a back side of the ROM cell (270 is in the backside when the figure is inverted) and the first source/drain region (262B); and a frontside contact (240A/VDB/250A, metal rails/contact layer/via contact, Para [0042],[0046], hereinafter “front”) between (front is between 262A and 210A) a power line (210A, power rails, Para [0042]) in a metal layer (rails are metal rails, Para [0031]) on a front side of the ROM cell (210A are in the front side when the figure is inverted) and the second source/drain region (262A), wherein the bit line is configured to provide a bit line signal to the on-cell (since 270 allows for electrical signals to be provided it will provide bit signal, Para [0046]), wherein the power line is configured to provide a power supply voltage signal to the on-cell (210A provides power, Para [0042]), and
wherein the bit line and the power line are aligned with each other in a vertical direction (270 and 210A are vertically aligned).
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Claim 20, Peng discloses (annotated Figs. 2A-2B above and Fig. 16) the integrated circuit of claim 19, wherein the bit line and the power line pass through a center of the on-cell (under BRI Fig. 2B shows 270 and 210A would pass through a center vertical line drawn in the Z-direction).
Claim 23, Peng discloses (annotated Figs. 2A-2B above and Fig. 16) the integrated circuit of claim 19, wherein the frontside contact (front) comprises: an active contact (VDB, contact layer, Para [0042]) on the second source/drain region (VDB is on the top surface of 262A); and an active via (250A, via contacts, Para [0042]) between the active contact and the power line (250A is between VDB and 210A).
Claim 24, Peng discloses (annotated Figs. 2A-2B above and Fig. 16) the integrated circuit of claim 19, wherein the backside contact (back) comprises an active via (275) between the first source/drain region and the bit line (275 is between 262B and 270). Claim 25, Peng discloses (annotated Figs. 2A-2B above and Fig. 16) the integrated circuit of claim 19, wherein the backside contact (back) comprises: an active contact (265B, metal diffusion, Para [0045]) on the first source/drain region (265B is on bottom surface 262B); and an active via (275, via contact, Para [0045]) between the active contact and the bit line (275 is between 265B and 270).
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sakai (US 2024/0395709).
Claim 10, Sakai discloses (Fig. 2) an integrated circuit comprising: a plurality of read only memory (ROM) cells (M00/M01/M10/M11, memory cells, Para [0047]); a plurality of bit lines (BL0/BL1, bit lines, Para [0048]) configured to provide bit line signals to the plurality of ROM cells (BL0/BL1 provide bit line signals); a plurality of word lines (WL0/WL1, word lines, Para [0050]) configured to provide word line signals to the plurality of ROM cells (WL0/WL1 provide word line signals); and a plurality of power lines (VSS, there are a plurality of power supplies, Para [0031] –[0032]) configured to provide a power supply voltage to the plurality of ROM cells (VSS applies ground power supply, Para [0048]), wherein the plurality of bit lines and the plurality of power lines are aligned with each other in a vertical direction (in Fig. 2, BL0/BL1 and VSS overlap with each other in a Y direction and are considered aligned in that overlap).
Allowable Subject Matter
Claims 8-9 and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Peng (US 2021/0391318), Sakai (US 2024/0395709), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 8, the frontside contact between the bit line and the third source/drain region; and the frontside contact between the bit line and the fourth source/drain region.
Regarding Claim 9, the backside contact between the power line and the third source/drain region; and the backside contact between the power line and the fourth source/drain region.
Regarding Claim 21, the frontside contact between the bit line and the third source/drain region; and the frontside contact between the bit line and the fourth source/drain region.
Regarding Claim 22, the backside contact between the power line and the third source/drain region; and the backside contact between the power line and the fourth source/drain region.
Claims 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Peng (US 2021/0391318), Sakai (US 2024/0395709), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 11, wherein the plurality of bit lines are in a metal layer on a front side of the plurality of ROM cells, and wherein the plurality of power lines are in a metal layer on a back side of the plurality of ROM cells.
Regarding Claim 12, wherein the plurality of bit lines are in a metal layer on a back side of the plurality of ROM cells, and wherein the plurality of power lines are in a metal layer on a front side of the plurality of ROM cells.
Regarding Claim 13, wherein the plurality of word lines are in a metal layer on a front side of the plurality of ROM cells.
Regarding Claim 14, wherein the plurality of word lines are in a metal layer on a back side of the plurality of ROM cells.
Regarding Claim 15 (from which claim 16 depends), a dummy pattern above the plurality of ROM cells and electrically separated from the plurality of ROM cells.
Regarding Claim 17 (from which claim 18 depends), wherein the first via and the second via are disposed side by side in the first horizontal direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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