Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18637017 filed on 04/16/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 06/04/2025 is acknowledged.
Allowable subject matter
Claims 6, 9 are objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Mitsuzuka et al. (US 2020/0335497).
With respect to dependent claims 6, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the semiconductor substrate has a trench filled with the gate structure, and the semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and including a portion facing the gate structure, the portion facing the gate structure having a distribution of plane orientations in the plan layout corresponding to the distribution of the threshold voltages”.
With respect to dependent claims 9, the cited prior art does not anticipate or make obvious, inter alia, the step of: “further comprising an emitter electrode having an edge, the emitter electrode being disposed on the semiconductor substrate, wherein the plurality of regions include the first region being the largest region of all the plurality of regions and at least one region having a higher threshold voltage than the first region, and in the plan layout, at least portion of the edge of the emitter electrode is disposed in the at least one region”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuzuka et al. (US 2020/0335497).
Regarding Independent claim 1, Mitsuzuka et al. teach a semiconductor device being an insulated gate bipolar transistor (Fig. 1, paragraph 0048) or a reverse-conducting insulated gate bipolar transistor, the semiconductor device comprising:
a semiconductor substrate (Fig. 3, element 10, paragraph 0045) including a drift layer (Fig. 3, element 18, paragraph 0083) having a first conductivity type; and
a gate structure including a gate electrode (Fig. 3, element 44, paragraph 0094) and a gate dielectric film (Fig. 3, element 42, paragraph 0094) for switching of the semiconductor device,
wherein a plan layout on the semiconductor substrate has a distribution of threshold voltages for the switching, and in a case where a histogram is defined by a plurality of bins each having a bin width of 100 mV for the threshold voltages and a plurality of frequencies corresponding to areas in the plan layout belonging to the respective bins, the plan layout includes a plurality of regions belonging to different bins of the plurality of bins, the plurality of regions include first to third regions, and the histogram has, based on a normal distribution, a distribution tailed on a low voltage side or on a high voltage side contiguously with the normal distribution (Fig. 3, paragraph 0100 discloses multiple areas/frequencies (gate portions 46-1 and 46-2) having plurality of bins (threshold voltage difference of 100mV). Although there are two regions cited, it would be obvious to one of ordinary skill in the art to have more than two regions with increment of 100mV threshold difference with the motivation to optimize snapback phenomenon (paragraph 0011). The threshold variance would have a normal variance and tailed distribution as the structure of the prior art is analogous to the instant application and wherein the threshold voltages are varied through gate dielectric thickness (Fig. 5, paragraph 0111-01112), varying the doping concentration of the base region (Fig. 6, element 14, paragraph 0113), heights (Figs. 4A-4B, paragraph 0105-0110) etc. similar to the instant application. The area of the first gate structure portion 46-1 having the first threshold voltage is smaller than the area of the second gate structure portion 46-2 having the second threshold voltage; therefore, it is highly probable that the distribution of the threshold voltage of the semiconductor device described in Mitsuzuka et al. is a "distribution in which the tail is drawn to the low voltage side" by the amount of the first threshold voltage with respect to the normal distribution of the second threshold voltage.).
Regarding claim 2, Mitsuzuka et al. teach wherein the semiconductor substrate further includes a base layer (Figs. 2 & 6, element 14, paragraph 0059) having a second conductivity type different from the first conductivity type, and the base layer has a distribution of impurity concentrations (paragraph 0113 discloses varying the doping concentration of the base region to vary the threshold voltages) in the plan layout corresponding to the distribution of the threshold voltages.
Regarding claim 3, Mitsuzuka et al. teach wherein the semiconductor substrate further includes a base layer (Figs. 2 & 6, element 14, paragraph 0059) having a second conductivity type different from the first conductivity type, and the base layer has a distribution of depths (Figs. 4A-4B & 6, paragraph 0105-0110) in the plan layout corresponding to the distribution of the threshold voltages.
Regarding claim 4, Mitsuzuka et al. teach wherein the semiconductor substrate further includes a source layer (Fig. 2, element 12, paragraph 0059) having the first conductivity type, and the source layer has a distribution of depths (Figs. 4A-4B & 7, paragraph 0105-0110, 0116-0119) in the plan layout corresponding to the distribution of the threshold voltages.
Regarding claim 5, Mitsuzuka et al. teach wherein the gate dielectric film has a distribution of thicknesses (Fig. 5, paragraph 0111-01112) in the plan layout corresponding to the distribution of the threshold voltages.
Regarding claim 7, Mitsuzuka et al. teach wherein the largest region of all the plurality of regions of the plan layout includes a center of the semiconductor substrate (since the distribution is a normal distribution the largest region would be central).
Regarding claim 8, Mitsuzuka et al. teach further comprising a gate wire 9Fig. 1, element 130, paragraph 0052) disposed on the semiconductor substrate, including a portion extending along one direction, and to apply a potential for the switching to the gate electrode, wherein a boundary between adjacent regions of the plurality of regions of the plan layout includes a portion extending along the one direction.
Regarding claim 10, Mitsuzuka et al. teach wherein in the plan layout, the semiconductor substrate has a rectangular shape (Fig. 1) having a long side and a short side, and in the plan layout, a boundary between adjacent regions of the plurality of regions extends along at least portion of an ellipse having a major axis along the short side of the rectangular shape (this would be an obvious design choice).
Regarding claim 12, Mitsuzuka et al. teach wherein the semiconductor substrate further includes, on the drift layer, a charge storage layer (Fig. 3, element 16, paragraph 0084) having the first conductivity type and having a higher impurity concentration than the drift layer, and the plurality of regions include a plurality of regions differing in impurity concentration of the charge storage layer.
Regarding claim 13, Mitsuzuka et al. teach wherein the drift layer of the semiconductor substrate includes a lifetime control layer (Fig. 9, element 92, paragraph 0122), and the plurality of regions include a region in which the lifetime control layer is disposed and a region in which the lifetime control layer is not disposed.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsuzuka et al. (US 2020/0335497) in view of Ueda et al. (JP 2017139292 A).
Regarding claim 11, Mitsuzuka et al. teach all of the limitations as discussed above.
Mitsuzuka et al. do not explicitly disclose wherein the semiconductor substrate has a distribution of internal stresses in the plan layout corresponding to the distribution of the threshold voltages.
It is well known in the art that threshold voltage changes due to stress as disclosed by Ueda et al. “In particular, in a vertical power element such as a MOSFET or IGBT, the threshold voltage changes due to stress”.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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