DETAILED ACTION
1. This Office action is in response to the RCE filed on 09 September 2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
4. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09 of September of 2026 has been entered.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claim(s) 1 – 3, 9 – 10 and 14 - 15 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1); (hereinafter Li and Lim).
Regarding claim 1, Li [e.g., Figs. 8, 12, 13A and 13C] discloses a power factor correction (PFC) control circuit [e.g., -- refer to Fig. 13C --], comprising: a pulse-width modulation (PWM) circuit configured to control a switch of a switching power converter [e.g., Drive circuit block controlling power switch]; a mode control circuit configured to select [e.g., Mode decision CCM/DCM block], based on a cyclic reference signal [e.g., cyclical signal A supplied by input A/D converter and voltage divider], a conduction mode from a plurality of conduction modes for the switching power converter [e.g., -- refer to Fig. 8 -- , Mode Decision block selects between CCM, CCM/DCM and DCM based on inductor current and cyclical signal A, p. 0054 recites “For full load and intermediate loads which cause constant CCM operation, depicted at the left of FIG. 8, the frequency is constant and the instantaneous iL oscillates around a current that follows the half-sinusoidal input voltage. When the load level causes a combination of CCM and DCM operation within a half line period, the frequency will be constant near the center of the half line period and will be significantly reduced towards the ends of the half line period, as illustrated in the center graph of FIG. 8.”] and to control a beginning of a switching cycle of the switching power converter based on the selected conduction mode [e.g., controls power switch according to mode selected at the beginning of each switching cycle, p. 0059 recites “Referring now to the flow chart of FIG. 12, in digital predictive control, the input voltage, Vin, inductor current, IL and output voltage, Vo, are sampled at the beginning of each switching cycle, the on-time and reference current, Ic, calculated and a determination is made whether the PFC circuit should be operated in CCM or DCM to deliver the next current pulse to the output filter and load.”]; a current-sense circuit [e.g., A/D converter connected between source Vin and input of the inductor] configured to generate an average current-sense signal [e.g., samples current flowing through the inductor and provides it to the processor, p. 0064 recites “The inductor/filter current is sampled and provided (preferably with A/D conversion) to a processor which calculates the off-time for the next switching cycle.”]; and a current regulation circuit [e.g., combination of internal control blocks (Mode decision block and Toff and Ton calculation blocks)] configured to compare the average current-sense signal against the cyclic reference signal [e.g., -- refer to Fig. 8 --, compares inductor current iL with half-sinusoidal input voltage (signal A)] to provide a regulation signal to the PWM circuit to regulate an average coil current of the switching power converter in each of the plurality of conduction modes [e.g., generates controls signals Ton and Toff to drive block, p. 0056 recites “More generally, however, FIG. 9 is intended to show that when the peak (or RMS, etc.) input voltage changes, the on-time profiles also changes accordingly based on the equation Ton(t)=(Vo-VinPsin(.omega.t))/Vofconst assuming the waveform remains sinusoidal or half-sinusoidal. The shape of the on-time profile will also change with the instantaneous voltage and differently shaped waveform will also result in differently shaped on-time profiles. The purpose of changing on-time profiles is to maintain a constant operating frequency at heavy load. The reason is that if an on-time profile corresponding to a lower input voltage is used for a higher input voltage, the inductor current ripple would be very large, leading to high RMS inductor current loss.”].
Li does not disclose a current-sense circuit configured to filter a current-sense signal that is indicative of a coil current of the switching power converter.
Lim [e.g., Fig. 2] teaches a current-sense circuit [e.g., resistor and capacitor (shown below) connected in series to source of transistor S generating signal vi to amplifier 140] configured to filter a current-sense signal that is indicative of a coil current of the switching power converter [e.g., p. 0023 recites “In an embodiment, the voltage across series resistor Rs is filtered to provide voltage vi for use by digital controller 114 to determine the current flowing through series inductor L.”].
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It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a current-sense circuit configured to filter a current-sense signal that is indicative of a coil current of the switching power converter as suggested by Lim to sample the current passing through the inductor at a specific sampling frequency of interest to be supplied to the processor [e.g., p. 0027 recites “Amplifier 140 has gain Kcs that scales the equivalent voltage vi to the input range of the ADC, such that the magnitude of the sensed equivalent voltage vis representing the sensed input current at the ADC is given by vis=KCSRsis=KCSRsig. The input current is sampled at a sampling frequency of fs,vin in kHz range.”].
Regarding claim 2, Li [e.g., Figs. 8, 12, 13A and 13C] discloses wherein the plurality of conduction modes for the switching power converter includes a continuous conduction mode [e.g., CCM] and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM), p.0065 recites "Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice- versa, as required for optimal frequency control within half line periods"].
Regarding claim 3, Li [e.g., Figs. 8, 12, 13A and 13C] discloses wherein the mode control circuit [e.g., mode decision block] is configured to cyclically select each of the plurality of conduction modes at different times within a period of a half-cycle of an AC line voltage received at an AC input of the switching power converter [e.g., determines operation at beginning of each cycle, abstract recites "The mode for controlling switching is preferably selected for each switching pulse within a half cycle of the cyclically varying input voltage". It continues on p.0065 recites "Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods"].
Regarding claim 9, Li [e.g., Figs. 8, 12, 13A and 13C] discloses a power factor correction (PFC) circuit [e.g., -- refer to Fig. 13C --], comprising: a boost converter including a switch and an inductor [e.g., combination of inductor and switch]; a feedback network [e.g., voltage divider connected between output voltage Vo and A/D converter] configured to generate a feedback signal representative of an output voltage of the boost converter [e.g., generated feedback based on output voltage Vo via output A/D converter]; and a power factor correction control circuit [e.g., remainder of circuit shown for digital Adaptive on-time control], comprising: a pulse-width modulation (PWM) circuit configured to control the switch of the boost converter [e.g., drive circuit for driving the switch of the power converter]; a mode control circuit [e.g., Mode decision CCM/DCM block] configured to select, based on a cyclic reference signal [e.g., cyclical signal A supplied by input A/D converter and voltage divider], a conduction mode from a plurality of conduction modes for the boost converter [e.g., -- refer to Fig. 8 -- , Mode Decision block selects between CCM, CCM/DCM and DCM based on inductor current and cyclical signal A, p. 0054 recites “For full load and intermediate loads which cause constant CCM operation, depicted at the left of FIG. 8, the frequency is constant and the instantaneous iL oscillates around a current that follows the half-sinusoidal input voltage. When the load level causes a combination of CCM and DCM operation within a half line period, the frequency will be constant near the center of the half line period and will be significantly reduced towards the ends of the half line period, as illustrated in the center graph of FIG. 8.”] and to control a beginning of a switching cycle of the boost converter based on the selected conduction mode [e.g., controls power switch according to mode selected at the beginning of each switching cycle, p. 0059 recites “Referring now to the flow chart of FIG. 12, in digital predictive control, the input voltage, Vin, inductor current, IL and output voltage, Vo, are sampled at the beginning of each switching cycle, the on-time and reference current, Ic, calculated and a determination is made whether the PFC circuit should be operated in CCM or DCM to deliver the next current pulse to the output filter and load.”]; a voltage regulation circuit [e.g., A/D converter connected to output voltage divider connected to Digital PI controller] configured to regulate the output voltage based at least in part on the feedback signal [e.g., p. 0064 recites "A voltage divider (and, preferably, an A/D converter) is preferably provided at both the input and output for adjustment of the control arrangement SO that the input and output voltages are coordinated for proper operation of the control arrangement"]; a current-sense circuit [e.g., A/D converter connected to the input of the inductor] configured to generate an average current-sense signal [e.g., configured to generate a current sense signal based on current flowing through the inductor, p. 0064 recites “The inductor/filter current is sampled and provided (preferably with A/D conversion) to a processor which calculates the off-time for the next switching cycle.”]; and a current regulation circuit [e.g., combination of internal control blocks (Mode decision block and Toff and Ton calculation block)] configured to compare the average current-sense signal against the cyclic reference signal [e.g., -- refer to Figs. 8 --, compares inductor current iL with half-sinusoidal input voltage (signal A)] to provide a regulation signal to the PWM circuit to regulate an average coil current of the boost converter in each of the plurality of conduction modes [e.g., generates controls signals Ton and Toff to drive block, p. 0056 recites “More generally, however, FIG. 9 is intended to show that when the peak (or RMS, etc.) input voltage changes, the on-time profiles also changes accordingly based on the equation Ton(t)=(Vo-VinPsin(.omega.t))/Vofconst assuming the waveform remains sinusoidal or half-sinusoidal. The shape of the on-time profile will also change with the instantaneous voltage and differently shaped waveform will also result in differently shaped on-time profiles. The purpose of changing on-time profiles is to maintain a constant operating frequency at heavy load. The reason is that if an on-time profile corresponding to a lower input voltage is used for a higher input voltage, the inductor current ripple would be very large, leading to high RMS inductor current loss.”].
Li does not disclose a current-sense circuit configured to filter a current-sense signal that is indicative of a coil current of the switching power converter.
Lim [e.g., Fig. 2] teaches a current-sense circuit [e.g., resistor and capacitor (shown below) connected in series to source of transistor S generating signal vi to amplifier 140] configured to filter a current-sense signal that is indicative of a coil current of the switching power converter [e.g., p. 0023 recites “In an embodiment, the voltage across series resistor Rs is filtered to provide voltage vi for use by digital controller 114 to determine the current flowing through series inductor L.”].
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It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a current-sense circuit configured to filter a current-sense signal that is indicative of a coil current of the switching power converter as suggested by Lim to sample the current passing through the inductor at a specific sampling frequency of interest to be supplied to the processor [e.g., p. 0027 recites “Amplifier 140 has gain Kcs that scales the equivalent voltage vi to the input range of the ADC, such that the magnitude of the sensed equivalent voltage vis representing the sensed input current at the ADC is given by vis=KCSRsis=KCSRsig. The input current is sampled at a sampling frequency of fs,vin in kHz range.”].
Regarding claim 10, Li [e.g., Figs. 8, 12, 13A and 13C] discloses wherein the plurality of conduction modes for the boost converter includes a continuous conduction mode [e.g., CCM] and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM)].
Regarding claim 14, Li [e.g., Figs. 8, 12, 13A and 13C] discloses a method for controlling a power factor correction (PFC) circuit [e.g., -- refer to FIG. 13C --, digital Adaptive on-time control], comprising: pulse-width modulating a switch of a switching power converter [e.g., Drive circuit block controlling power switch]; cyclically selecting, based on a cyclic reference signal [e.g., cyclical signal A supplied by input A/D converter], each of a plurality of conduction modes for the switching power converter at different times within each half-cycle of an AC line voltage [e.g., controls power switch according to mode selected at the beginning of each switching cycle, p. 0059 recites “Referring now to the flow chart of FIG. 12, in digital predictive control, the input voltage, Vin, inductor current, IL and output voltage, Vo, are sampled at the beginning of each switching cycle, the on-time and reference current, Ic, calculated and a determination is made whether the PFC circuit should be operated in CCM or DCM to deliver the next current pulse to the output filter and load.”] received at an AC input of the switching power converter [e.g., cyclical signal A supplied by input A/D converter]; generate an average current-sense signal [e.g., A/D converter connected between Vin source and input of the inductor]; and regulating an average coil current of the switching power converter with a current regulation circuit [e.g., controls current flowing through the inductor by combination of internal control blocks (Mode decision block and Toff and Ton calculation block)], based on a comparison of the average current-sense signal against the cyclic reference signal, during each of the plurality of conduction modes [e.g., generates controls signals Ton and Toff to drive block, p. 0056 recites “More generally, however, FIG. 9 is intended to show that when the peak (or RMS, etc.) input voltage changes, the on-time profiles also changes accordingly based on the equation Ton(t)=(Vo-VinPsin(.omega.t))/Vofconst assuming the waveform remains sinusoidal or half-sinusoidal. The shape of the on-time profile will also change with the instantaneous voltage and differently shaped waveform will also result in differently shaped on-time profiles. The purpose of changing on-time profiles is to maintain a constant operating frequency at heavy load. The reason is that if an on-time profile corresponding to a lower input voltage is used for a higher input voltage, the inductor current ripple would be very large, leading to high RMS inductor current loss.”].
Li does not disclose filtering a current-sense signal that is indicative of a coil current of the switching power converter.
Lim [e.g., Fig. 2] teaches filtering a current-sense signal [e.g., resistor and capacitor (shown below) connected in series to source of transistor S generating signal vi to amplifier 140] that is indicative of a coil current of the switching power converter [e.g., p. 0023 recites “In an embodiment, the voltage across series resistor Rs is filtered to provide voltage vi for use by digital controller 114 to determine the current flowing through series inductor L.”].
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It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with filtering a current-sense signal that is indicative of a coil current of the switching power converter as suggested by Lim to sample the current passing through the inductor at a specific sampling frequency of interest to be supplied to the processor [e.g., p. 0027 recites “Amplifier 140 has gain Kcs that scales the equivalent voltage vi to the input range of the ADC, such that the magnitude of the sensed equivalent voltage vis representing the sensed input current at the ADC is given by vis=KCSRsis=KCSRsig. The input current is sampled at a sampling frequency of fs,vin in kHz range.”].
Regarding claim 15, Li [e.g., Figs. 8, 12, 13A and 13C] discloses wherein the plurality of conduction modes includes a continuous conduction mode and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM)].
8. Claim(s) 4, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1) and Clark et al (US Pub. No. 2014/0097808 A1); (hereinafter Li, Lim and Clark).
Regarding claims 4 and 11, Li discloses the claimed invention except for wherein the mode control circuit is configured to select the conduction mode based at least in part on an output power of the switching power converter.
Clark [e.g., Figs. 6 and 8] teaches wherein the mode control circuit [e.g., MCM (Mixed Conduction mode) control 16] is configured to select the conduction mode based at least in part on an output power of the switching power converter [e.g., separate mode used on depending on output power p. 0078 - 0079 recites "At an output power loading of Pout=49 W, where pure DCM operation over the entire line cycle is observable, the DCM flag successfully specified constant DCM operation over the entire line cycle. There were no false triggers leading to a change in the reported mode of operation. [0079] At an output power of Pout=98 W, generally for the majority of the line cycle, proper detection of DCM operation and CCM operation was specified"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the mode control circuit is configured to select the conduction mode based at least in part on an output power of the switching power converter as suggested by Clark to provide accurate detection of zero inductor current using simple computational calculation with minimal resource.
Regarding claim 17, Li discloses the claimed invention except for selecting a conduction mode based at least in part on an output power of the switching power converter.
Clark [e.g., Figs. 6 and 8] teaches selecting a conduction mode based at least in part on an output power of the switching power converter [e.g., p. 0078 0079 recites "At an output power loading of Pout=49 W, where pure DCM operation over the entire line cycle is observable, the DCM flag successfully specified constant DCM operation over the entire line cycle. There were no false triggers leading to a change in the reported mode of operation. [0079] At an output power of Pout=98 W, generally for the majority of the line cycle, proper detection of DCM operation and CCM operation was specified."]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with selecting a conduction mode based at least in part on an output power of the switching power converter as suggested by Clark to provide accurate detection of zero inductor current using simple computational calculation with minimal resource.
9. Claim(s) 5, 6, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1) and Melanson (US Patent No. 7,719,248 B1; (hereinafter Li, Lim and Melanson).
Regarding claim 5, Li discloses the claimed invention except for a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter.
Melanson [e.g., Fig. 23] teaches a threshold generator [e.g., target current generator 300] configured to generate a minimum coil current threshold [e.g., configured to generate target current itarget, col. 8 lines 24 – 27 recites “Digital output product value 350 is fed into DAC 307, and DAC 307 converts the digital output product value 350 into a reference voltage V(itarget) that is representative of the target current value (itarget).”]; and a comparator [e.g., comparator 303] configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter [e.g., compares current Itarget and current Isense, col. 20 lines 48-60 recites "FIG. 23 shows a high-level block diagram of the PFC controller214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current / target is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 6, Li discloses the claimed invention except for send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes.
Melanson [e.g., Fig. 23] teaches send a trigger signal to the PWM circuit [e.g., switching control signal Cs0] to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes [e.g., col. 21 lines 1 8 recites "A CCM/DCM decision block 2314 is coupled to multiplexer 2310, and CCM/DCM decision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the outputofMUX2310, and gate drive 2312 provides as its output the switching control signal CSO"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes as suggested by Melanson to select between operating the switch mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 12, Li discloses the claimed invention except for a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes.
Melanson [e.g., Fig. 23] teaches a threshold generator [e.g., target current generator 300] configured to generate a minimum coil current threshold [e.g., configured to generate target current itarget, col. 8 lines 24 – 27 recites “Digital output product value 350 is fed into DAC 307, and DAC 307 converts the digital output product value 350 into a reference voltage V(itarget) that is representative of the target current value (itarget).”]; and a comparator [e.g., comparator 303] configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter [e.g., compares current Itarget and current Isense, col. 20 lines 48-60 recites "FIG. 23 shows a high-level block diagram of the PFC controller214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current / target is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3"]; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit [e.g., switching control signal Cs0] to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes [e.g., col. 21 lines 1 8 recites "A CCM/DCMdecision block 2314 is coupled to multiplexer 2310, and CCM/DCMdecision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the output of MUX2310, and gate drive 2312 provides as its output the switching control signal CSO"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 18, Li et al discloses the claimed invention except for generating a minimum coil current threshold; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold.
Melanson [e.g., Fig. 23] teaches generating a minimum coil current threshold [e.g., target current generator 300 configured to generate minimum current threshold iccm]; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter [e.g., compares current Itarget and current Isense, col. 20 lines 48-60 recites "FIG. 23 shows a high-level block diagram of the PFC controller214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current / target is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3"]; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold [e.g., col. 21 lines 1 8 recites "A CCM/DCM decision block 2314 is coupled to multiplexer 2310, and CCM/DCM decision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the output of MUX2310, and gate drive 2312 provides as its output the switching control signal CSO"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with generating a minimum coil current threshold; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
10. Claim(s) 7, 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1) and Castelli (US Pub. No. 2016/0020692 A1); (hereinafter Li, Lim and Castelli).
Regarding claim 7, Li discloses the claimed invention except for a valley counter configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero.
Castelli [e.g., Fig. 9] teaches a valley counter [e.g., zero current detection block (ZCD) 60] configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero [e.g., configured to detect when current in inductor reaches zero p. 0048 recites "A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so-called "valley skipping mode" in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal Isense and provides pulses to a DCM managing circuit 62 when the inductor current/ is null. In this case, the switch 18 is not turned on even if the inductor current/ is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current/ during the off time interval"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a valley counter configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero as suggested by Castelli to attain a high efficiency even at low load conditions and also when a discontinuous current mode (DCM) control is implemented.
Regarding claim 8, Li discloses the claimed invention except for wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes.
Castelli [e.g., Fig. 9] teaches wherein the mode control circuit [e.g., closed loop control circuit 26B] is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle [e.g., controls SW18 via Gate DRV 36] in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes [e.g., in response when DCM is selected e.g., p. 0048 recites "An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so called "valley skipping mode" in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal Isense and provides pulses to a DC managing circuit 62 when the inductor current/ is null. In this case, the switch 18 is not turned on even if the inductor current/ is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current/ during the off-time interval. Only when the charge voltage VLOOP nullifies, the PWM zero-detection comparator 38 issues a pulse to the DCM managing circuit 62, that on its turn sets the SR flip-flop 42."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes as suggested by Castelli for improved efficiency at low power (when controlling in DCM) and similar performances at high power (when controlling in CCM).
Regarding claim 13, Li discloses the claimed invention except for a valley counter configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero; and the mode control circuit is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes.
Castelli [e.g., Fig. 9] teaches a valley counter [e.g., zero current detection block (ZCD) 60] configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero [e.g., configured to detect when current flowing through the inductor reaches zero p. 0048 recites "A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so called "valley skipping mode" in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal/ sense and provides pulses to a DCM managing circuit 62 when the inductor current/ is null."]; and the mode control circuit [e.g., closed-loop control circuit 26B] is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle [e.g., controls SW18 via Gate DRV36] in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes [e.g., in response to mode selected e.g., p. 0048 recites "An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. … In this case, the switch 18 is not turned on even if the inductor current/ is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current/ during the off-time interval. Only when the charge voltage VLOOP nullifies, the PWM zero-detection comparator 38 issues a pulse to the DCMmanaging circuit 62, that on its turn sets the SR flip-flop 42"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a valley counter configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero; and the mode control circuit is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes as suggested by Castelli to attain a high efficiency even at low load conditions and also when a discontinuous current mode (DCM) control is implemented.
11. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1) and Dong (US Pub. No. 2022/0263402 A1); (hereinafter Li, Lim and Dong).
Regarding claim 16, Li [e.g., Figs. 8, 12, 13A and 13C] discloses generating the cyclic reference signal to have a shape of a full-wave rectified AC signal that is in phase with the AC line voltage [e.g., cyclical signal A supplied by input A/D converter, p. 0054 recites “… the frequency is constant and the instantaneous iL oscillates around a current that follows the half-sinusoidal input voltage.”].
Li does not disclose comparing the cyclic reference signal against a plurality of thresholds.
Dong [e.g., Figs. 3A] teaches comparing the cyclic reference signal against a plurality of thresholds [e.g., compares frequency of signal with Vth1, Vth2, and Vth3, p. 0043 recites "Referring to FIGS. 3A-3B, the switching frequency F(Vin, lin, Vo, lo) is calculated according to input voltage Vin, the input current lin, the output voltage Vo and the output current lo, and F(Vin, lin, Vo, lo) is compared with the preset switching frequency range. During time periods TO-T1 and T6-T7, the switching frequency F(Vin, lin, Vo, lo) is greater than or equal to the maximum frequency threshold Fmax, then the working mode of the AC-DC conversion circuit is controlled to the DCM, as shown in FIG. 3A and FIG. 4; or the working mode of the bridgeless PFC circuit is controlled to be the CCM, as shown in FIG. 3B and FIG. 4. And the actual switching frequency Factual is equal to the maximum frequency threshold Fmax during the time periods TO-T1 and T6-T7."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with comparing the cyclic reference signal against a plurality of thresholds as suggested by Dong to limit the actual switching frequency of the bridgeless PFC to be lower than the maximum frequency threshold to reduce the driving loss and facilitate.
12. Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2012/0014148 A1) in view of Lim et al (US Pub. No. 2016/0190912 A1) and Twelkemeijer (US Pub. No. 2023/0086600 A1); (hereinafter Li, Lim and Twelkemeijer).
Regarding claim 19, Li discloses the claimed invention except for detecting a first valley of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a critical conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal.
Twelkemeijer [e.g., Figs. 1 and 2] teaches detecting a first valley [e.g., -- refer to second mode 204 in Fig. 2 -- , detects zero crossing 228] of an oscillation signal present at a node of the switching power converter [e.g., oscillating current flowing through inductor] after a coil current of the switching power converter has reached zero [when inductor current reaches zero]; and when operating the switching power converter in a critical conduction mode [e.g., while operating at BCM (Boundary Conduction Mode)], turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal [e.g., p. 0042 recites "The second mode 204 is commonly referred to as BCM(Boundary Conduction Mode) or sometimes as CCM (Critical Conduction Mode). In this mode, the primary and secondary stroke are very similar except that the gate of the converter switch is only turned ON when the inductor current reaches zero. The initial zero crossing 220 is the beginning of the primary stroke 222 of the ON time in the BCM mode 204. At the peak current time 224 the transition is made and the switch is set to OFF."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with detecting a first valley of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a critical conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal as suggested by Twelkemeijer et al to avoid mains filter oscillations and decrease the audible noise.
Regarding claim 20, Li discloses the claimed invention except for detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a discontinuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal.
Twelkemeijer [e.g., Fig. 1 and 2] teaches detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero [e.g., -- refer to Fig. 2 third mode 206 -- detect multiple zero current crossings]; and when operating the switching power converter in a discontinuous conduction mode [e.g., while operating at DCM (Discontinuous Conduction Mode)], turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal [e.g., p. 0043 recites "The third mode 206 is commonly referred to as DCM(Discontinuous Conduction Mode) because the inductor current, or input current, has a dead time interval during which no power is delivered. There is an added delay after the secondary stroke before the next primary stroke. In the DCM mode 206, the first stroke begins at a zero inductor current crossing time 230 with the switch turned ON. The primary stroke 232 extends through a current rise time and a peak inductor current 234 at which the switch ON time is ended and the inductor current falls during the second stroke 236 to a zero inductor current crossing 238. Instead of starting the next period at the end of this power phase, the switch remains off or an additional time 240 during a ringing phase. The end of the ringing phase is the end of the period 242 at which time the next power phase begins with another primary stroke 232 by turning the switch to ON with a drive signal from the cycle-by-cycle converter"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a discontinuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal as suggested by Twelkemeijer et al to avoid mains filter oscillations and decrease the audible noise.
Examiner’s Note
13. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
14. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
15. Applicant’s arguments with respect to claim(s) 1, 9 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
