DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 3, 9 - 10 and 14 - 15 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2012/0014148 A1; (hereinafter Li et al).
Regarding claim 1, Li et al [e.g., Fig. 13C] discloses a power factor correction (PFC) control circuit [e.g., boost power converter], comprising: a pulse-width modulation (PWM) circuit [e.g., drive block] configured to control a switch of a switching power converter [e.g., drives switch of the boost power converter]; a mode control circuit [e.g., Mode decision CCM/DCM block] configured to select a conduction mode from a plurality of conduction modes for the switching power converter [e.g., configured to select between discontinuous conduction mode (DCM) or constant current mode (CCM)] and to control a beginning of a switching cycle of the switching power converter based on the selected conduction mode [e.g., p. 0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”]; and a current regulation circuit [e.g., digital PI and Multiplier via average reference current Ic] configured to provide a regulation signal [e.g., reference current Ic] to the PWM circuit to regulate an average coil current of the switching power converter in each of the plurality of conduction modes [e.g., p. 0063 recites “For CCM operation, the average inductor current can be controlled to be the same as the current reference if the inductor current at the end of a switching cycle is one-half the ripple voltage lower than the current reference as shown in FIG. 13A. For DCM operation, the area of the inductor current is controlled to be the same as the area of the rectangle formed by Ic and the duration of the time span between consecutive sampling points as shown by hatching of the waveforms in FIG. 13B”. It continues on p. 0064 recites “Signals representing input and output voltages are provided to a processor for calculating both the on-time and off-time for a particular switching cycle as well as the signal representing the input voltage being supplied to a conduction mode decision control. (The calculated on-time signal is also fed back to the conduction mode decision control.) These signals. after passing the signal representing the output through a proportional-integral (PI) compensator where it is compared with a reference, are also multiplied to determine an average reference current, Ic, which is also input to the conduction mode decision control that applies the control law discussed above. The inductor/filter current is sampled and provided (preferably with A/D conversion) to a processor which calculates the off-time for the next switching cycle. It should be noted that the on-time and off-time are computed for each switching cycle but the particular algorithm discussed above chosen to compute the off-time will be controlled responsive to the conduction mode decision which is also responsive to the result of the on-time calculation. The on-time and off-time calculation results are provided to an appropriate drive circuit for driving the switch(es) of the power converter”].
Regarding claim 2, Li et al [e.g., Fig. 13C] discloses wherein the plurality of conduction modes for the switching power converter includes a continuous conduction mode [e.g., CCM] and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM), p.0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”].
Regarding claim 3, Li et al [e.g., Fig. 13C] discloses wherein the mode control circuit [e.g., mode decision block] is configured to cyclically select each of the plurality of conduction modes at different times within a period of a half-cycle of an AC line voltage received at an AC input of the switching power converter [e.g., abstract recites “The mode for controlling switching is preferably selected for each switching pulse within a half cycle of the cyclically varying input voltage”. It continues on p.0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”]
Regarding claim 9, Li et al [e.g., Fig. 13C] discloses a power factor correction (PFC) circuit [e.g., boost power converter], comprising: a boost converter including a switch and an inductor [e.g., inductor with current IL and switch]; a feedback network [e.g., voltage divider connected between Vo and A/D converter] configured to generate a feedback signal representative of an output voltage of the boost converter [e.g., p. 0064 recites “A voltage divider (and, preferably, an A/D converter) is preferably provided at both the input and output for adjustment of the control arrangement so that the input and output voltages are coordinated for proper operation of the control arrangement”]; and a power factor correction control circuit [e.g., remainder of circuit shown], comprising: a pulse-width modulation (PWM) circuit configured to control the switch of the boost converter [e.g., drive circuit for driving the switch of the power converter with switch]; a mode control circuit [e.g., Mode decision CCM/DCM block] configured to select a conduction mode from a plurality of conduction modes for the boost converter [e.g., configured to select between discontinuous conduction mode (DCM) or constant current mode (CCM)] and to control a beginning of a switching cycle of the boost converter based on the selected conduction mode [e.g., p. 0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”]; a voltage regulation circuit [e.g., A/D converter connected to output voltage divider] configured to regulate the output voltage based at least in part on the feedback signal [e.g., p. 0064 recites “A voltage divider (and, preferably, an A/D converter) is preferably provided at both the input and output for adjustment of the control arrangement so that the input and output voltages are coordinated for proper operation of the control arrangement”]; and a current regulation circuit [e.g., digital PI and multiplier generating average reference current Ic] configured to provide a regulation signal to the PWM circuit [e.g., reference current Ic] to regulate an average coil current of the boost converter in each of the plurality of conduction modes [e.g., p. 0063 recites “For CCM operation, the average inductor current can be controlled to be the same as the current reference if the inductor current at the end of a switching cycle is one-half the ripple voltage lower than the current reference as shown in FIG. 13A. For DCM operation, the area of the inductor current is controlled to be the same as the area of the rectangle formed by Ic and the duration of the time span between consecutive sampling points as shown by hatching of the waveforms in FIG. 13B”. It continues on p. 0064 recites “Signals representing input and output voltages are provided to a processor for calculating both the on-time and off-time for a particular switching cycle as well as the signal representing the input voltage being supplied to a conduction mode decision control. (The calculated on-time signal is also fed back to the conduction mode decision control.) These signals. after passing the signal representing the output through a proportional-integral (PI) compensator where it is compared with a reference, are also multiplied to determine an average reference current, Ic, which is also input to the conduction mode decision control that applies the control law discussed above”].
Regarding claim 10, Li et al [e.g., Fig. 13C] discloses wherein the plurality of conduction modes for the boost converter includes a continuous conduction mode [e.g., CCM] and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM), p.0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”].
Regarding claim 14, Li et al [e.g., Fig. 13C] discloses a method for controlling a power factor correction (PFC) circuit [e.g., boost power converter], comprising: pulse-width modulating a switch of a switching power converter [e.g., drive circuit for driving the switch of the power converter]; cyclically selecting each of a plurality of conduction modes [e.g., Mode decision CCM/DCM configured to cyclically select between discontinuous conduction mode (DCM) or constant current mode (CCM)] for the switching power converter at different times within each half-cycle of an AC line voltage received at an AC input of the switching power converter [e.g., abstract recites “The mode for controlling switching is preferably selected for each switching pulse within a half cycle of the cyclically varying input voltage”. It continues on p. 0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”]; and regulating an average coil current [e.g., regulates average coil current via reference current IC] of the switching power converter with a current regulation circuit during each of the plurality of conduction modes [e.g., p. 0063 recites “For CCM operation, the average inductor current can be controlled to be the same as the current reference if the inductor current at the end of a switching cycle is one-half the ripple voltage lower than the current reference as shown in FIG. 13A. For DCM operation, the area of the inductor current is controlled to be the same as the area of the rectangle formed by Ic and the duration of the time span between consecutive sampling points as shown by hatching of the waveforms in FIG. 13B”. It continues on p. 0064 recites “Signals representing input and output voltages are provided to a processor for calculating both the on-time and off-time for a particular switching cycle as well as the signal representing the input voltage being supplied to a conduction mode decision control. (The calculated on-time signal is also fed back to the conduction mode decision control.) These signals. after passing the signal representing the output through a proportional-integral (PI) compensator where it is compared with a reference, are also multiplied to determine an average reference current, Ic, which is also input to the conduction mode decision control that applies the control law discussed above”].
Regarding claim 15, Li et al [e.g., Fig. 13C] discloses wherein the plurality of conduction modes includes a continuous conduction mode and one or more of a critical conduction mode and a discontinuous conduction mode [e.g., conduction mode selected between discontinuous conduction mode (DCM) or constant current mode (CCM), p.0065 recites “Current sampling at the beginning of each switching cycle and determining if that switching cycle will be operated in DCM (where the off-time will be extended) or CCM (where off-time will not be extended) allows shifting between DCM and CCM, or vice-versa, as required for optimal frequency control within half line periods”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of US Pub. No. 2014/0097808 A1; (hereinafter Li et al and Clark et al).
Regarding claim 4 , Li et al discloses the claimed invention except for to select the conduction mode based at least in part on an output power of the switching power converter.
Clark et al [e.g., Figs. 6 and 8] teaches to select the conduction mode based at least in part on an output power of the switching power converter [e.g., separate mode used on depending on output power p. 0078 - 0079 recites “At an output power loading of Pout=49 W, where pure DCM operation over the entire line cycle is observable, the DCMflag successfully specified constant DCM operation over the entire line cycle. There were no false triggers leading to a change in the reported mode of operation. [0079] At an output power of Pout=98 W, generally for the majority of the line cycle, proper detection of DCM operation and CCM operation was specified”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with to select the conduction mode based at least in part on an output power of the switching power converter as suggested by Clark et al to provide a cost-effective ZCD detection solution, while avoiding or improving on existing detection structures and methods.
Regarding claim 11 , Li et al discloses the claimed invention except for to select the conduction mode based at least in part on an output power of the switching power converter.
Clark et al [e.g., Figs. 6 and 8] teaches to select the conduction mode based at least in part on an output power of the switching power converter [e.g., p. 0078 - 0079 recites “At an output power loading of Pout=49 W, where pure DCM operation over the entire line cycle is observable, the DCMflag successfully specified constant DCM operation over the entire line cycle. There were no false triggers leading to a change in the reported mode of operation. [0079] At an output power of Pout=98 W, generally for the majority of the line cycle, proper detection of DCM operation and CCM operation was specified”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with to select the conduction mode based at least in part on an output power of the switching power converter as suggested by Clark et al to provide a cost-effective ZCD detection solution, while avoiding or improving on existing detection structures and methods.
Regarding claim 17, Li et al discloses the claimed invention except for selecting each of the plurality of conduction modes comprises selecting a conduction mode based at least in part on an output power of the switching power converter.
Clark et al [e.g., Figs. 6 and 8] teaches selecting each of the plurality of conduction modes comprises selecting a conduction mode based at least in part on an output power of the switching power converter.
[e.g., p. 0078 - 0079 recites “At an output power loading of Pout=49 W, where pure DCM operation over the entire line cycle is observable, the DCMflag successfully specified constant DCM operation over the entire line cycle. There were no false triggers leading to a change in the reported mode of operation. [0079] At an output power of Pout=98 W, generally for the majority of the line cycle, proper detection of DCM operation and CCM operation was specified.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with selecting each of the plurality of conduction modes comprises selecting a conduction mode based at least in part on an output power of the switching power converter as suggested Clark et al to provide a cost-effective ZCD detection solution, while avoiding or improving on existing detection structures and methods.
Claim(s) 5 - 6, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of US Patent No. 7,719,248 B1; (hereinafter Li et al and Melanson).
Regarding claim 5, Li et al discloses the claimed invention except for a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter.
Melanson [e.g., Fig. 23] teaches a threshold generator [e.g., target current generator 300] configured to generate a minimum coil current threshold [e.g., configured to generate minimum current threshold iccm]; and a comparator [e.g., comparator 303] configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter [e.g., compares current I target and current I sense, column 20 lines 48 - 60 recites “FIG. 23 shows a high-level block diagram of the PFC controller 214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current itarget is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 6, Li et al discloses the claimed invention except for a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes.
Melanson [e.g., Fig. 23] teaches a trigger signal to the PWM circuit [e.g., switching control signal Cs0] to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes [e.g., column 21 lines 1 - 8 recites “A CCM/DCM decision block 2314 is coupled to multiplexer 2310, and CCM/DCM decision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the output of MUX 2310, and gate drive 2312 provides as its output the switching control signal CS0”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 12, Li et al discloses the claimed invention except for a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes.
Melanson [e.g., Fig. 23] teaches a threshold generator [e.g., target current generator 300] configured to generate a minimum coil current threshold [e.g., configured to generate minimum current threshold iccm]; and a comparator [e.g., comparator 303] configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter [e.g., compares current I target and current I sense, column 20 lines 48 - 60 recites “FIG. 23 shows a high-level block diagram of the PFC controller 214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current itarget is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3”]; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit [e.g., switching control signal Cs0] to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes [e.g., column 21 lines 1 - 8 recites “A CCM/DCM decision block 2314 is coupled to multiplexer 2310, and CCM/DCM decision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the output of MUX 2310, and gate drive 2312 provides as its output the switching control signal CS0”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with a threshold generator configured to generate a minimum coil current threshold; and a comparator configured to compare the minimum coil current threshold against a current-sense signal indicating a coil current of the boost converter; and wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the comparator when a continuous conduction mode has been selected from among the plurality of conduction modes as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Regarding claim 18, Li et al discloses the claimed invention except for generating a minimum coil current threshold; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold.
Melanson [e.g., Fig. 23] teaches generating a minimum coil current threshold [e.g., target current generator 300 configured to generate minimum current threshold iccm]; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter [e.g., compares current I target and current I sense, column 20 lines 48 - 60 recites “FIG. 23 shows a high-level block diagram of the PFC controller 214 in FIGS. 2A and 2B for enabling the switch-mode stage/converter (e.g., switch-mode boost stage 202A and 2028) to operate in CCM or DCM. As discussed earlier, the switch-mode boost stage 202A and 202B operate in CCM or DCM depending on whether the target current itarget is above or below a minimum (min) current threshold iCCM. In FIG. 23, target current generator 300 and comparator 303 are the same as previously disclosed in FIG. 3”]; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold [e.g., column 21 lines 1 - 8 recites “A CCM/DCM decision block 2314 is coupled to multiplexer 2310, and CCM/DCM decision block 2314 outputs a control signal to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met. A gate drive 2312 is coupled to the output of MUX 2310, and gate drive 2312 provides as its output the switching control signal CS0”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with generating a minimum coil current threshold; comparing the minimum coil current threshold against a current-sense signal indicating a coil current of the switching power converter; and when operating the switching power converter in a continuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to the current-sense signal reaching the minimum coil current threshold as suggested by Melanson to select between operating the switch-mode converter between CCM and DCM depending on which condition of the target current has been met.
Claim(s) 7 - 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of US Pub. No. 2016/0020692 A1; (hereinafter Li et al and Castelli).
Regarding claim 7, Li et al discloses the claimed invention except for a valley counter configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero.
Castelli [e.g., Fig. 9] teaches a valley counter [e.g., zero current detection block (ZCD) 60] configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero [e.g., configured to detect when current in inductor reaches zero p. 0048 recites “An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so-called “valley skipping mode” in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal Isense and provides pulses to a DCM managing circuit 62 when the inductor current I is null. In this case, the switch 18 is not turned on even if the inductor current I is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current I during the off-time interval”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with a valley counter configured to detect valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero as suggested by Castelli to attain a high efficiency even at low load conditions and also when a discontinuous current mode (DCM) control is implemented
Regarding claim 8, Li et al discloses the claimed invention except for wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes.
Castelli [e.g., Fig. 9] teaches wherein the mode control circuit [e.g., closed-loop control circuit 26B] is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle [e.g., controls SW18 via Gate DRV 36] in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes [in response when DCM is selected e.g., p. 0048 recites “An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so-called “valley skipping mode” in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal Isense and provides pulses to a DCM managing circuit 62 when the inductor current I is null. In this case, the switch 18 is not turned on even if the inductor current I is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current I during the off-time interval. Only when the charge voltage VLOOP nullifies, the PWM zero-detection comparator 38 issues a pulse to the DCM managing circuit 62, that on its turn sets the SR flip-flop 42. According to this implementation, the off-time modulation in DCM condition is still managed by means of the proposed charge/discharge mechanism implemented by the OFF time predictor 32 without any discontinuity between CCM and DCM operation”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the mode control circuit is configured to send a trigger signal to the PWM circuit to control the beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes as suggested by Castelli for improved efficiency at low power (when controlling in DCM) and similar performances at high power (when controlling in CCM).
Regarding claim 13, Li et al discloses the claimed invention except for a valley counter configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero; and the mode control circuit is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes.
Castelli [e.g., Fig. 9] teaches a valley counter [e.g., zero current detection block (ZCD) 60] configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero [e.g., configured to detect when current in inductor reaches zero p. 0048 recites “An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so-called “valley skipping mode” in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal I sense and provides pulses to a DCM managing circuit 62 when the inductor current I is null. In this case, the switch 18 is not turned on even if the inductor current I is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current I during the off-time interval”].; and the mode control circuit [e.g., closed-loop control circuit 26B] is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle [e.g., controls SW18 via Gate DRV 36] in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes [e.g., in response when DCM is selected e.g., p. 0048 recites “An alternate closed-loop control circuit 26B of this disclosure may be equipped with means for managing a DCM functioning mode, as shown in the embodiment of FIG. 9. The control circuit 26B includes a PWM 34B according to a second embodiment. A zero current detection block (ZCD) 60 is added to the PWM 34B for implementing the so-called “valley skipping mode” in DCM operating condition, illustrated by the exemplary time graphs depicted in FIG. 10. The zero current detection block 60 receives in input the sense signal Isense and provides pulses to a DCM managing circuit 62 when the inductor current I is null. In this case, the switch 18 is not turned on even if the inductor current I is null and thus the charge voltage VLOOP does not replicate the waveform of the inductor current I during the off-time interval. Only when the charge voltage VLOOP nullifies, the PWM zero-detection comparator 38 issues a pulse to the DCM managing circuit 62, that on its turn sets the SR flip-flop 42”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with a valley counter configured to detect valleys of an oscillation signal present at a node of the boost converter after a coil current of the boost converter has reached zero; and the mode control circuit is configured to send a trigger signal to the PWM circuit to control a beginning of the switching cycle in response to the valley counter when a critical conduction mode or a discontinuous conduction mode has been selected from among the plurality of conduction modes as suggested by Castelli to attain a high efficiency even at low load conditions and also when a discontinuous current mode (DCM) control is implemented
Claim(s) 19 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of US Pub. No. 2023/0086600 A1; (hereinafter Li and Twelkemeijer et al).
Regarding claim 19, Li et al discloses the claimed invention except for detecting a first valley of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a critical conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal.
Twelkemeijer et al [e.g., Fig. 1 and 2] teaches detecting a first valley [e.g., detects when inductor current reaches zero -- refer to second mode 204 in Fig. 2 --] of an oscillation signal present at a node of the switching power converter [e.g., oscillating current flowing through inductor] after a coil current of the switching power converter has reached zero [when inductor current reaches zero]; and when operating the switching power converter in a critical conduction mode [e.g., while operating at BCM (Boundary Conduction Mode)], turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal [e.g., p. 0042 recites “The second mode 204 is commonly referred to as BCM (Boundary Conduction Mode) or sometimes as CrCM (Critical Conduction Mode). In this mode, the primary and secondary stroke are very similar except that the gate of the converter switch is only turned ON when the inductor current reaches zero. The initial zero crossing 220 is the beginning of the primary stroke 222 of the ON time in the BCM mode 204. At the peak current time 224 the transition is made and the switch is set to OFF. The inductor current decreases during the secondary stroke 226 until a zero crossing 228. The period in BCM mode may be increased by increasing the ON time and thereby increasing duration of the primary stroke and the peak voltage. The secondary stroke will accordingly become longer as well. Increasing the period also increases the inductor current as the current becomes higher during the longer primary stroke. The described controller of FIG. 1 may be used to change the ON time of a primary or master converter to increase or decrease the inductor current and the period.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with detecting a first valley of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a critical conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting the first valley of the oscillation signal as suggested by Twelkemeijer et al to avoid mains filter oscillations and decrease the audible noise.
Regarding claim 20, Li et al discloses the claimed invention except for detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a discontinuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal.
Twelkemeijer et al [e.g., Fig. 1 and 2] teaches detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero [e.g., detect multiple zero current crossings -- refer to Fig. 2 third mode 206 -- ]; and when operating the switching power converter in a discontinuous conduction mode [e.g., while operating at DCM (Discontinuous Conduction Mode)], turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal [e.g., p. 0043 recites “The third mode 206 is commonly referred to as DCM (Discontinuous Conduction Mode) because the inductor current, or input current, has a dead time interval during which no power is delivered. There is an added delay after the secondary stroke before the next primary stroke. In the DCM mode 206, the first stroke begins at a zero inductor current crossing time 230 with the switch turned ON. The primary stroke 232 extends through a current rise time and a peak inductor current 234 at which the switch ON time is ended and the inductor current falls during the second stroke 236 to a zero inductor current crossing 238. Instead of starting the next period at the end of this power phase, the switch remains off for an additional time 240 during a ringing phase. The end of the ringing phase is the end of the period 242 at which time the next power phase begins with another primary stroke 232 by turning the switch to ON with a drive signal from the cycle-by-cycle converter”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li et al with detecting a plurality of valleys of an oscillation signal present at a node of the switching power converter after a coil current of the switching power converter has reached zero; and when operating the switching power converter in a discontinuous conduction mode, turning the switch on to initiate a switching cycle of the switching power converter in response to detecting a second or subsequent valley of the oscillation signal as suggested by Twelkemeijer et al to avoid mains filter oscillations and decrease the audible noise.
Examiner’s Note
13. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
14. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
15. Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
16. The following is a statement of reasons for the indication of allowable subject matter:
17. The primary reason for the indication of the allowability of claim 16 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein cyclically selecting each of the plurality of conduction modes comprises: generating a cyclic reference signal with a shape of a full-wave rectified AC signal that is in phase with the AC line voltage; and comparing the cyclic reference signal against a plurality of thresholds.”
Conclusion
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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