DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 Modification A in the reply filed on 27 July 2026 is acknowledged. Claims 10 and 13 are withdrawn in the reply. However, claims 7, 8, and 18 are also drawn to non-elected Modifications B and C, and are therefore also withdrawn from consideration. Claims 1-6, 9, 11-12, 14-17, and 19-20 are examined on the merits in this Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 11-12, 14-17, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seung Min Song et al. (US 20240355878 A1; hereinafter Song).
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Regarding Claim 1, Song discloses a semiconductor device (Fig. 2A) comprising:
a first transistor (200; ¶0018) comprising a first gate region (204; ¶0020);
a second transistor (201; ¶0018) comprising a second gate region (104; ¶0022), wherein the second transistor (201) is stacked over the first transistor (200); and
a conductive contact (108; ¶0026) disposed between and contacting a surface of the first gate region (top of 204) and a surface of the second gate region (bottom of 104), wherein the surface of the second gate region (bottom of 104) is disposed opposite the surface of the first gate region (top of 204) (as shown in Fig. 2A; ¶0026).
Regarding Claim 2, Song discloses the semiconductor device of claim 1, wherein:
the first transistor (200) comprises a first plurality of stacked channel layers (208; ¶0020);
the second transistor (201) comprises a second plurality of stacked channel layers (212; ¶0022);
the conductive contact (108) overlaps at least part of the first plurality of stacked channel layers (208) and at least part of the second plurality of stacked channel layers (212) (as shown in Fig. 2A; they overlap in the Z direction).
Regarding Claim 3, Song discloses the semiconductor device of claim 1, wherein the conductive contact (108) is (electrically) connected to a conductive liner layer (work function layer located between the channels and gate electrode metallic layers {¶0033}, wherein the gate electrode is all around the channel {¶0025} and therefore the work function layer is disposed on a side surface of the gate electrode) disposed on a side surface of the second gate region.
Regarding Claim 4, Song discloses the semiconductor device of claim 3, wherein the conductive liner layer (work function layer) is disposed between the side surface of the second gate region (as above) and a side surface of a gate isolation region (wherein a gate insulator {¶0023} is a gate isolation region and is on a side surface {of GAA channels} and between the work function layer {of the gate electrode} and the channels {¶0023}).
Regarding Claim 9, Song discloses the semiconductor device of claim 1, wherein a width of the conductive contact (a width of 108, as measured in Fig. 2A, between a side of 104 that is recessed into 108 and the side of 108 adjacent the insulating layer 216, labeled W1 in the annotated Fig. 2A) is less than a width of the first gate region (204) and a width of the second gate region (104) (labeled W2 in annotated Fig. 2A).
Regarding Claim 11, Song discloses the semiconductor device of claim 1, further comprising a dielectric layer (216; ¶0028) between the surface of the first gate region (top of 204) and the surface of the second gate region (bottom of 104) (216 is located and/or exists between these surfaces), wherein the conductive contact (108) is disposed through the dielectric layer (as shown in Fig. 2A; 108 is disposed through 216 at the location of 108).
Regarding Claim 12, Song discloses the semiconductor device of claim 1, wherein the first (200) and the second transistors (201) comprise nanosheet transistors (they each comprise nanosheet channels 208 and 212, as described in ¶0034).
Regarding Claim 14, Song discloses a semiconductor device (Fig. 2A) comprising:
a first gate region (204; ¶0020); a second gate region (104; ¶0022) stacked over the first gate region;
a dielectric layer (216; ¶0028) disposed between the first gate region (204) and the second gate region (104) (216 is disposed and/or exists at a location between the gate regions); and
a conductive contact (108; ¶0028) disposed in the dielectric layer (216) between the first gate region (204) and the second gate region (104), wherein the conductive contact (108) contacts the first gate region (204) and the second gate region (104) (physically and electrically; ¶0026).
Regarding Claim 15, Song discloses the semiconductor device of claim 14, wherein the conductive contact (108) overlaps a channel layer (208 or 212; ¶0020 or ¶0022) of at least one of the first gate region (204) and the second gate region (104) (they overlap in the Z direction as shown in Fig. 2A).
Regarding Claim 16, Song discloses the semiconductor device of claim 14, wherein the conductive contact (107) is connected (electrically) to a conductive liner layer disposed on a side surface of the second gate region (the conductive liner is a work function layer located between the channels and gate electrode metallic layers {¶0033}, wherein the gate electrode is all around the channel {¶0025} and therefore the work function layer is disposed on a side surface of the gate electrode).
Regarding Claim 17, Song discloses the semiconductor device of claim 16, wherein the conductive liner layer (work function layer) is disposed between the side surface of the second gate region (as above) and a side surface of a gate isolation region (wherein a gate insulator {¶0023} is a gate isolation region and is on a side surface {of GAA channels} and between the work function layer {of the gate electrode} and the channels {¶0023}).
Regarding Claim 19, Song discloses a semiconductor device (Fig. 2A) comprising:
a first nanosheet transistor (200; ¶0018, ¶0034) comprising a first gate region (204; ¶0020);
a second nanosheet transistor (201; ¶0018; ¶0034) comprising a second gate region (104; ¶0022), wherein the second nanosheet transistor (201) is stacked over the first nanosheet transistor (200) (Fig. 2A); and
a conductive contact (108; ¶0026) disposed between the first nanosheet transistor (200) and the second nanosheet transistor (201), wherein the conductive contact (108) contacts a surface of the first gate region (top of 204) and a surface of the second gate region (bottom of 104), wherein the surface of the second gate region (bottom of 104) is disposed opposite the surface of the first gate region (top of 204) (as shown in Fig. 2A; ¶0026).
Regarding Claim 20, Song discloses the semiconductor device of claim 19, wherein the conductive contact (108) is disposed between a channel layer (208; ¶0020) of the first nanosheet transistor (200) and a channel layer (212; ¶0022) of the second nanosheet transistor (201) (as shown in fig. 2A).
Claims 1-2, 9, 11-12, 14-15, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hung-Li Chiang et al. (US 20240130100 A1; hereinafter Chiang).
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Regarding Claim 1, Chiang discloses a semiconductor device (Fig. 2B) comprising:
a first transistor (PD1; ¶0032) comprising a first gate region (G01; ¶0032);
a second transistor (PU1; ¶0024) comprising a second gate region (G05; ¶0032), wherein the second transistor (PU1) is stacked over the first transistor (PD1); and
a conductive contact (VC; ¶0050) disposed between and contacting a surface of the first gate region (top of PD1) and a surface of the second gate region (bottom of PU1), wherein the surface of the second gate region is disposed opposite the surface of the first gate region (as shown in Fig. 2B).
Regarding Claim 2, Chiang discloses the semiconductor device of claim 1, wherein:
the first transistor (PD1) comprises a first plurality of stacked channel layers (C01; ¶0032);
the second transistor (PU1) comprises a second plurality of stacked channel layers (C05; ¶0036);
the conductive contact (VC) overlaps at least part of the first plurality of stacked channel layers (C01) and at least part of the second plurality of stacked channel layers (C05) (as shown in Fig. 2B in the D3 direction).
Regarding Claim 9, Chiang discloses the semiconductor device of claim 1, wherein a width of the conductive contact (VC) is less than a width of the first gate region (G01) and a width of the second gate region (G05) (as shown in Fig. 2B).
Regarding Claim 11, Chiang discloses the semiconductor device of claim 1, further comprising a dielectric layer (ESL; ¶0047) between the surface of the first gate region (top of G01) and the surface of the second gate region (bottom of G05), wherein the conductive contact (VC) is disposed through the dielectric layer (ESL) (as shown in Fig. 2B).
Regarding Claim 12, Chiang discloses the semiconductor device of claim 1, wherein the first (PD1) and the second (PU1) transistors comprise nanosheet transistors (¶0052).
Regarding Claim 14, Chiang discloses a semiconductor device (Fig. 2B) comprising:
a first gate region (G01; ¶0032); a second gate region (G05; ¶0032) stacked over the first gate region (G01);
a dielectric layer (ESL; ¶0047) disposed between the first gate region (G01) and the second gate region (G05); and
a conductive contact (VC; ¶0050) disposed in the dielectric layer (ESL) between the first gate region (G01) and the second gate region (G05), wherein the conductive contact (VC) contacts the first gate region and the second gate region (as shown in Fig. 2B).
Regarding Claim 15, Chiang discloses the semiconductor device of claim 14, wherein the conductive contact (VC) overlaps a channel layer (C01 or C05; ¶0032. ¶0036) of at least one of the first gate region (G01) and the second gate region (G05).
Regarding Claim 19, Chiang discloses a semiconductor device (Fig. 2B) comprising:
a first nanosheet transistor (PD1; ¶0024, ¶0052) comprising a first gate region (G01; ¶0032);
a second nanosheet transistor (PU1; ¶0024, ¶0052) comprising a second gate region (G05; ¶0032), wherein the second nanosheet transistor (PU1) is stacked over the first nanosheet transistor (PD1); and
a conductive contact (VC; ¶0050) disposed between the first nanosheet transistor and the second nanosheet transistor (as shown in Fig. 2B), wherein the conductive contact (VC) contacts a surface of the first gate region (top of G01) and a surface of the second gate region (bottom of G05), wherein the surface of the second gate region is disposed opposite the surface of the first gate region (as shown in Fig. 2B).
Regarding Claim 20, Chiang discloses the semiconductor device of claim 19, wherein the conductive contact (VC) is disposed between a channel layer (C01; ¶0032) of the first nanosheet transistor (PD1) and a channel layer (C05; ¶0036) of the second nanosheet transistor (PU1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Seung Min Song et al. (US 20240355879 A1; hereinafter Song879).
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Regarding Claim 3, Chiang discloses the semiconductor device of claim 1, but does not expressly disclose wherein the conductive contact is connected to a conductive liner layer disposed on a side surface of the second gate region.
In the same field of endeavor, Song879 teaches a device comprising stacked nanosheet transistors (Fig. 2C) with an upper gate electrode (112; ¶0022) stacked over a lower gate electrode (110; ¶0020) and electrically connected by a conductive contact (122b; ¶0043), wherein each gate electrode comprises a conductive liner work function layer (242 and 240; ¶0020 and ¶0022) surrounding all sides of a conductive metal gate electrode material (246 and 244; ¶0022 and ¶0020).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the work function conductive liner surrounding all the sides of the gate electrode material (in the manner of Song879) in the device of Chiang in order to provide/adjust the desired threshold voltage for each respective transistor.
This combination would result in the conductive work function liner of Song879 (240/242) lining the sides of gate regions (G01, G03, G09, G05) of Chiang, resulting in the conductive contact (VC) being connected (electrically) to the conductive liner (work function conductive liner 240/242 of Song879, as modified) disposed on a side surface(s) of the second gate region (sides of G05).
Regarding Claim 4, modified Chiang teaches the semiconductor device of claim 3, wherein the conductive liner layer (240/242 of Song879 lining the gate regions G01, G03, G05, and G09) is disposed between the side surface of the second gate region (right side of G05) and a side surface of a gate isolation region (left side of ILD {¶0047} which isolates gates G05 and G07, as shown in Fig. 2B).
Regarding Claim 5, modified Chiang teaches the semiconductor device of claim 4, further comprising an additional conductive liner layer (as modified by Song879, the additional conductive work function liner lining the sides of gate G09) disposed on an additional side surface of the gate isolation region (right side of ILD) and on a side surface of third gate region (as modified, the conductive work function liner lines the left side surface of third gate G07 {¶0039}) adjacent the second gate region (G05).
Regarding Claim 6, modified Chiang discloses the semiconductor device of claim 5, wherein the additional conductive liner layer (as modified, the conductive work function liner layer lining the sides of G07) is electrically isolated from the conductive liner layer (they are isolated by ILD) and the additional side surface of the gate isolation region (right side of ILD) is located opposite the side surface of the gate isolation region (left side of ILD) (as shown in Fig. 2B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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