Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10, and 18-19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sharma et al. (US Patent Pub 20190393222 A1).
Regarding Claim 1, Sharma teaches a semiconductor device comprising:
a bit line on a substrate (Fig. 1A and 1B, bit line 105. Paragraph 0024 teaches the device is formed on a substrate);
a bonding layer stacked on the bit line (Fig. 1A and 1B, bonding layer 103)
a first conductive connection pattern stacked on the bonding layer, so that the bonding layer is vertically between the bit line and the first conductive connection pattern (Fig. 1A and 1B, first conductive connection pattern 105i stacked on bonding layer 104 and arranged so that a portion of 104 is vertically between the bit line 105 and 105i);
a channel stacked on the first conductive connection pattern, the channel including a single crystalline semiconductor material (Fig. 1A and 1B, channel 115. Paragraph 0026 teaches 115 can be formed of a single crystalline semiconductor material);
a second conductive connection pattern contacting the bit line and the first conductive connection pattern (Fig. 1A and 1B, second conductive connection pattern 108);
a gate electrode on the bit line, the gate electrode being spaced apart from the channel and the first conductive connection pattern (Fig. 1A and 1B, gate electrode 112, which is spaced apart from 115 and 105i);
and a capacitor stacked on the channel (Fig. 1A and 1B, capacitor 120 stacked on 112).
Regarding Claim 2, Sharma teaches the semiconductor device according to claim 1, wherein the second conductive connection pattern contacts an upper surface of the bit line and a sidewall of the first conductive connection pattern (Fig. 1A and 1B teaches second conductive connection pattern 108 contacts an upper surface of bit line 105 and a sidewall of 105i).
Regarding Claim 3, Sharma teaches the semiconductor device according to claim 2, wherein the bonding layer is formed of an insulative material (Sharma, paragraph 0031 teaches the bonding layer 103 is formed of a dielectric material, which is insulative).
Regarding Claim 4, Sharma teaches the semiconductor device according to claim 1, wherein a sidewall of the second conductive connection pattern is aligned with a sidewall of the channel in a vertical direction perpendicular to an upper surface of the substrate (Fig. 1B teaches the second conductive connection pattern 108 is aligned with a sidewall of channel 115 in a vertical direction perpendicular to the upper surface of the substrate).
Regarding Claim 5, Sharma teaches The semiconductor device according to claim 1, wherein the bit line is one of a plurality of bit lines spaced apart from each other in a second direction parallel to an upper surface of the substrate, each of the plurality of bit lines extending in a first direction parallel to the upper surface of the substrate and crossing the second direction and connected to a respective bonding layer and a respective second conductive connection pattern (Fig. 1A and 1B teach a plurality of bit lines 105 spaced apart in a second direction parallel to an upper surface of the substrate and extending in a first direction parallel to the upper surface of the substrate, and crossing the second direction, each connected to a respective bonding layer and respective second conductive connection pattern),
wherein two bit lines of the plurality of bit lines neighboring in the second direction form a bit line pair, and a plurality of bit line pairs are arranged in the second direction ((Fig. 1A teaches two bit lines 105 neighboring in a second direction. Paragraph 0033 of applicant's own specification teaches that two bit lines adjacent to each other in the second direction may be referred to as a bit line pair. Therefore, Fig. 1A teaches a plurality of bit line pairs arranged in the second direction.)
and wherein for each bit line pair, a first sidewall of a first bit line faces a second sidewall of a second bit line, one second conductive connection pattern is disposed on the first sidewall of the first bit line, and another second conductive connection pattern is disposed on the second sidewall of the second bit line (Fig. 1A and 1B).
Regarding Claim 6, Sharma teaches the semiconductor device according to claim 1, further comprising a source/drain pattern between the first conductive connection pattern and the channel, the source/drain pattern including doped polysilicon (Fig. 1A and 1B, source/drain pattern 116. Paragraph 0026 teaches the composition of the source/drain pattern, which can include doped polysilicon).
Regarding Claim 7, Sharma teaches the semiconductor device according to claim 1, further comprising a source/drain pattern and a landing pad stacked between the channel and the capacitor (Fig. 1A and 1B, source/drain pattern 118 and landing pad 121 stacked between the channel 115 and the capacitor 120).
Regarding Claim 10, Sharma teaches a semiconductor device comprising:
a bit line on a substrate (Fig. 1A and 1B, bit line 105);
an insulative bonding layer stacked on the bit line (Fig. 1A and 1B, insulative bonding layer 103);
a first source/drain pattern stacked on the bonding layer, so that the bonding layer is between the bit line and the first source/drain pattern, the first source/drain pattern including doped polysilicon (Fig. 1A and 1B, first source/drain pattern 116. Paragraph 0026 teaches the composition of the source/drain pattern, which can include doped polysilicon);
a channel on the first source/drain pattern, the channel including a single crystalline semiconductor material (Fig. 1A and 1B, channel 115. Paragraph 0026 teaches 115 can be formed of a single crystalline semiconductor material);
a conductive pattern vertically between the channel and the bonding layer (Fig. 1A and 1B, conductive pattern 108);
a conductive connection pattern contacting the bit line and the conductive pattern (Fig. 1A and 1B, conductive connection pattern 108);
a gate electrode on the bit line, the gate electrode being spaced apart from the channel and the conductive pattern (Fig. 1A and 1B, gate electrode 112);
and a capacitor on the channel (Fig. 1A and 1B, capacitor 120).
Regarding Claim 18, Sharma teaches a semiconductor device comprising:
a lower circuit pattern on a substrate (Fig. 2 and paragraph 0028 teaches a lower circuit pattern on a substrate 261. Paragraph 0036 teaches a plurality of DRAM cells are formed on the substrate, and Fig. 1A and 1B teach the structure of the DRAM cells (paragraph 0025));
bit lines on the lower circuit pattern, each of the bit lines extending in a first direction parallel to an upper surface of the substrate, and the bit lines being spaced apart from each other in a second direction parallel to the upper surface of the substrate and crossing the first direction ((Fig. 1A, 1B, and 2 teach bit lines 105 extending in a first direction parallel to an upper surface of the substrate and spaced apart in a second direction parallel to the upper surface of the substrate and crossing the first direction))
bonding structures on the bit lines, respectively (Fig. 1A, 1B, and 2 teach bonding structures 104 on the bit lines);
a plurality of first conductive connection patterns, each first conductive connection pattern on a respective bonding structure (Fig. 1A, 1B, and 2 teach a plurality of first conductive connection patterns 105i on respective bonding structures 104. Each of the DRAM cells would have a 105i structure, therefore there are a plurality of 105i structures);
a plurality of first source/drain patterns, each first source/drain pattern on a respective first conductive connection pattern (Fig. 1A, 1B, and 2 teach a plurality of first source/drain patterns 116, each on a respective first conductive connection pattern 105i);
a plurality of channels, each channel on a respective first source/drain pattern (Fig. 1A, 1B, and 2 teach a plurality of channels 115, each on a respective first source/drain pattern 116);
a plurality of second conductive connection patterns, each second conductive connection pattern contacting a respective bit line of the bit lines and a respective first conductive pattern of the plurality of first conductive connection patterns (Fig. 1A, 1B, and 2 teach a plurality of second conductive connection patterns 108, each of 108 contacting a respective bit line 105 and a respective 105i);
a plurality of gate electrodes, each gate electrode on a respective bit line, each of the gate electrodes extending in the second direction, and the gate electrodes being spaced apart from each other in the first direction (Fig. 1A, 1B, and 2 teach a plurality of gate electrodes 112, each gate electrode on a respective bit line and extending in the second direction and spaced apart from each other in the first direction);
a gate insulation pattern on a sidewall of each of the gate electrodes and contacting each of the channels (Fig. 1A, 1B, and 2 teach a gate insulation pattern 114 on a sidewall of each of 112 and contacting each channel 115);
a plurality of second source/drain patterns, each second source/drain pattern on a respective channel (Fig. 1A, 1B, and 2 teach a plurality of second source/drain patterns 118, each on a respective channel 115);
a plurality of landing pads, each landing pad on a respective second source/drain pattern (Fig. 1A, 1B, and 2 teach a plurality of landing pads 121, each on a respective second source/drain pattern 118);
and a plurality of capacitors, each capacitor on a respective landing pad (Fig. 1A, 1B, and 2 teach a plurality of capacitors 120, each on a respective landing pad 121).
Regarding Claim 19, Sharma teaches the semiconductor device according to claim 17, wherein two bit lines of the bit lines neighboring in the second direction form a bit line pair, and a plurality of bit line pairs are arranged in the second direction (Fig. 1A and 1B teaches two bit lines 105 neighboring in a second direction. Paragraph 0033 of applicant's own specification teaches that two bit lines adjacent to each other in the second direction may be referred to as a bit line pair. Therefore, Fig. 1A and 1B teach a plurality of bit line pairs arranged in the second direction. Because a plurality of DRAM cells are arranged on a substrate in the second direction, the plurality of bit line pairs are arranged in the second direction),
and wherein for each bit line pair, a first sidewall of a first bit line faces a second sidewall of a second bit line, one second conductive connection pattern is disposed on the first sidewall of the first bit line, and another second conductive connection pattern is disposed on the second sidewall of the second bit line (Fig.1A and 1B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8, 11-13, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma as applied to claims 1-7, 10, and 18-19 above, and further in view of Lee et al. (US Patent Pub 20220102352 A1).
Regarding Claim 8, Sharma teaches the semiconductor device according to claim 1, wherein the first conductive connection pattern includes a metal, and a conductive pattern between the first conductive connection pattern and the channel (Sharma, Fig. 1A, 1B, and paragraph 0030 teach the first conductive connection pattern 105i includes a metal (such as Cu). Paragraph 0037 and Fig. 1A and 1B teach conductive pattern 108 formed of Cu, which is between the first conductive connection pattern 105i and the channel 115).
Sharma fails to teach the conductive pattern is an ohmic contact pattern, the ohmic contact pattern including a metal silicide.
However, Lee teaches an ohmic contact pattern, the ohmic contact pattern including a metal silicide (Lee, Fig 16 and paragraph 0095 teach contact pattern LP is an ohmic contact pattern that may be formed of a metal silicide or alternatively Cu. Applicant’s own specification (paragraph 0041) teaches an ohmic contact pattern is formed of a metal silicide, therefore LP is an ohmic contact pattern).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Lee into the method of Sharma by forming the semiconductor device comprising an ohmic contact pattern between the first conductive connection pattern and the channel, the ohmic contact pattern including a metal silicide. The ordinary artisan would have been motivated to modify Sharma in the manner set forth above for at least the purpose of utilizing known semiconductor materials to ensure successful device fabrication.
Furthermore, art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07.
Regarding Claim 11, Sharma teaches the semiconductor device according to claim 10, wherein the conductive pattern contacts a sidewall of the first source/drain pattern (Sharma, Fig. 1A and 1B and paragraph 0037 teaches conductive pattern 108 formed of a metal such as Cu touches a sidewall of the first source/drain pattern).
Sharma fails to specifically teach the contact pattern is an ohmic contact pattern including a metal silicide.
However, Lee teaches a semiconductor memory device wherein the contact pattern is an ohmic contact pattern and includes a metal silicide (Lee, Fig 16 and paragraph 0095 teach contact pattern LP is an ohmic contact pattern that may be formed of a metal silicide or alternatively Cu. Applicant’s own specification (paragraph 0041) teaches an ohmic contact pattern is formed of a metal silicide, therefore LP is an ohmic contact pattern).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Lee into the method of Sharma by forming the semiconductor device comprising an ohmic contact pattern, the ohmic contact pattern including a metal silicide. The ordinary artisan would have been motivated to modify Sharma in the manner set forth above for at least the purpose of utilizing known semiconductor materials to ensure successful device fabrication.
Furthermore, art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07.
Regarding Claim 12, Sharma in view of Lee teaches the semiconductor device according to claim 11, wherein the channel contacts an upper surface of the ohmic contact pattern (Sharma, Fig. 1A and 1B, channel 115 contacts upper surface of 108).
Regarding Claim 13, Sharma in view of Lee teaches the semiconductor device according to claim 11, wherein a sidewall of the conductive connection pattern is aligned with a sidewall of the channel in a vertical direction perpendicular to an upper surface of the substrate (Sharma, Fig. 1B teaches a sidewall of the conductive connection pattern 108 is aligned with a sidewall of the channel 115 in a vertical direction perpendicular to an upper surface of the substrate).
Regarding Claim 15, Sharma in view of Lee teaches the semiconductor device according to claim 11, further comprising a second source/drain pattern and a landing pad stacked between the channel and the capacitor (Sharma, Fig. 1A and 1B, second source/drain pattern 118 and landing pad 121 stacked between the channel 115 and capacitor 120).
Regarding Claim 16, Sharma in view of Lee teaches the semiconductor device according to claim 11, wherein the conductive connection pattern includes a metal (Sharma, paragraph 0030 teaches the conductive connection pattern 105i includes a metal).
Regarding Claim 20, Sharma teaches the semiconductor device according to claim 18, wherein the gate insulation pattern contacts sidewalls in the first direction of the first source/drain pattern on each of the bonding structures (Sharma, Fig. 1A and 1B, gate insulation pattern 114 contacting the first source/drain pattern 116 in the first direction on each of the bonding structures 104).
Sharma Fails to teach the semiconductor device wherein the gate insulation pattern contacts sidewalls in the first direction of each of the bonding structures and the first conductive connection pattern.
However, Lee teaches a semiconductor memory device wherein the gate insulation pattern contacts sidewalls in the first direction of each of the bonding structures and the first conductive connection pattern (Lee, Fig. 16 teaches gate insulation pattern Gox contacting the sidewalls in the first direction of each of the bonding structures 141 and the first conductive connection pattern WL1).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Lee into the method of Sharma by forming the semiconductor memory device wherein the gate insulation pattern contacts sidewalls in the first direction of each of the bonding structures and the first conductive connection pattern. The ordinary artisan would have been motivated to modify Sharma in the manner set forth above for at least the purpose of reducing leakage current (Lee, paragraph 0220).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Lee as applied to claims 8, 11-13, 15-16, and 20 above, and further in view of Karda et al. (US patent Pub 20230178661 A1).
Regarding Claim 17, Sharma in view of Lee teaches the semiconductor device according to claim 11, having a bonding layer on the bit line (Sharma, Fig. 1A and 1B and paragraph 0036 teach a bonding layer formed of silicon dioxide on the bit line).
Sharma in view of Lee fail to teach the bonding layer includes silicon carbonitride.
However, Karda teaches a semiconductor memory device wherein the bonding layer includes silicon carbonitride (Karda, Fig. 1A, bonding layer 108. Paragraph 0026 teaches 108 may be formed of silicon carbonitride or alternatively silicon dioxide).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Karda into the method of Sharma in view of Lee by forming the semiconductor memory device wherein the bonding layer includes silicon carbonitride. The ordinary artisan would have been motivated to modify Sharma in view of Lee in the manner set forth above for at least the purpose of utilizing known semiconductor materials to ensure successful device fabrication.
Furthermore, art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07.
Claim(s) 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma as applied to claims 1-7, 10, and 18-19 above, and further in view of Karda et al. (US patent Pub 20230178661 A1).
Regarding Claim 9, Sharma teaches the semiconductor device according to claim 1, having a bonding layer on the bit line (Sharma, Fig. 1A and 1B and paragraph 0036 teach a bonding layer formed of silicon dioxide on the bit line).
Sharma fails to teach the bonding layer includes silicon carbonitride.
However, Karda teaches a semiconductor memory device wherein the bonding layer includes silicon carbonitride (Karda, Fig. 1A, bonding layer 108. Paragraph 0026 teaches 108 may be formed of silicon carbonitride or alternatively silicon dioxide).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Karda into the method of Sharma by forming the semiconductor memory device wherein the bonding layer includes silicon carbonitride. The ordinary artisan would have been motivated to modify Sharma in the manner set forth above for at least the purpose of utilizing known semiconductor materials to ensure successful device fabrication.
Furthermore, art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07.
Regarding Claim 14, Sharma in view of Karda teaches the semiconductor device according to claim 9, wherein the bit line is one of a plurality of bit lines spaced apart from each other in a second direction parallel to an upper surface of the substrate, each of the plurality of bit lines extending in a first direction parallel to the upper surface of the substrate and crossing the second direction (Fig. 1A and 1B teaches a plurality of bit lines 105 spaced apart from each other in a second direction parallel to an upper surface of the substrate, each of the plurality of bit lines extending in a first direction parallel to the upper surface of the substrate and crossing the second direction),
wherein two bit lines of the plurality of bit lines neighboring in the second direction form a bit line pair, and a plurality of bit line pairs are arranged in the second direction (Fig. 1A teaches two bit lines 105 neighboring in a second direction. Paragraph 0033 of applicant's own specification teaches that two bit lines adjacent to each other in the second direction may be referred to as a bit line pair. Therefore, Fig. 1A teaches a plurality of bit line pairs arranged in the second direction),
and wherein for each bit line pair, a first sidewall of a first bit line faces a second sidewall of a second bit line, one conductive connection pattern is disposed on the first sidewall of the first bit line, and another conductive connection pattern is disposed on the second sidewall of the second bit line (Fig. 1A and 1B).
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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