Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, claims 1-12, 16-20 in the reply filed on 07/21/2026 is acknowledged. The traversal is on the ground(s) that there is no significant burden to review all of the claims. This is not found persuasive because the differences between the invention groups constitute a significant search burden due to their differences in scope. In the case of an independent claim being found in the conditions for allowance, any withdrawn claim with the limitations of the allowable independent claims will be eligible for rejoinder.
Claim Rejections - 35 USC § 112
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, limitations regarding “upper” and “lower” and “lowermost” etc. are recited but no reference point by which to decide this spatial relationship is provided. In addition, the limitation “lower surfaces of the etch stop pattern and the third spacer” leaves the meaning ambiguous as to whether the lower surfaces refer to both the etch stop pattern and the third spacer, or just the etch stop pattern. Appropriate correction is needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 8-9, 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al.(US 20220139927 A1, hereafter Chang).
Regarding Claim 1, Chang discloses:
A semiconductor device(Figs. 3-5) comprising:
An active pattern(Fig. 3 [ACT]) on a substrate(Fig. 4 [100]);
A first conductive contact(Fig. 4 [146]) on a central portion of the active pattern(Fig. 3 [ACT]);
a bit line structure(Fig. 4 [140]) on the first conductive contact(Fig. 4 [146]);
a spacer structure(Fig. 4 [150/160SP]) on sidewalls of the bit line structure(Fig. 4 [140]) and on sidewalls of the first conductive contact(Fig. 4 [146]), the spacer structure(Fig. 4 [150/160SP]) including a first spacer(fig. 4 [151]), a second spacer(Fig. 4 [152/153]), an etch stop pattern(Fig. 4 [154]) and a third spacer(Fig. 4 [160SP]) sequentially stacked in a horizontal direction parallel to an upper surface of the substrate(Fig. 4 [100]);
a second conductive contact(Fig. 4 [120]) on an end portion of the active pattern(Fig. 3 [ACT]); and
a capacitor(Fig. 4 [190]) on the second conductive contact(Fig. 4 [190]),
wherein a lowermost surface of the first spacer(Fig. 4 [151]) is lower than a lowermost surface of the second spacer(Fig. 4 [152/153]), and lower surfaces of the etch stop pattern(Fig. 4 [154]) and third spacer(Fig. 4 [160SP]) are higher than the lowermost surface of the second spacer(Fig. 4 [152/153]).
Regarding Claim 4, Chang discloses:
The second conductive contact(Fig. 4 [120]) includes a lower portion(Fig. 4 [120]) and an upper portion(Fig. 4 [160]) arranged along a vertical direction perpendicular to the upper surface of the substrate(Fig. 4 [100]), and
Wherein a width of the upper portion(Fig. 4 [160]) of the second conductive contact(fig. 4 [120/160]) in the first horizontal direction is less than a width of the lower portion(Fig. 4 [120]) of the second conductive contact(Fig. 4 [120/160]) in the first horizontal direction.
Regarding Claim 5, Chang discloses:
Lower surfaces of the etch stop pattern(Fig. 4 [154]) and the third spacer(Fig. 4 [160SP]) contact an upper surface of the lower portion(Fig. 4 [120]) of the second conductive contact(Fig. 4 [120/160]).
Regarding Claim 6, Chang discloses:
A fence pattern(Fig. 5 [170]) including a lower portion(Fig. 5 See figure below) and an upper portion(Fig. 5 See figure below) arranged along the vertical direction,
Wherein a width of the upper portion(Fig. 5 See figure below) of the fence pattern(Fig. 5 [170]) in the first horizontal direction is less than a width of the lower portion(Fig. 5 See figure below) of the fence pattern(Fig. 5 [170]) in the horizontal direction.
Regarding Claim 8, Chang discloses:
A buffer stack(Fig. 4 [130/141]) between the substrate(Fig. 4 [100]) and the bit line structure(Fig. 4 [140]), an upper surface of the buffer stack(Fig. 4 [130/141]) being coplanar with an upper surface of the first conductive contact(Fig. 4 [146]),
Wherein the bit line structure(Fig. 4 [140]) extends in a second direction(into the page) parallel to the upper surface of the substrate(Fig. 4 [100]), and the spacer structure(Fig. 4 [150/160SP]) is disposed on each of opposite sidewalls of the bit line structure(Fig. 4 [140]) and the first conductive contact(Fig. 4 [146]) in a first direction parallel to the upper surface of the substrate(Fig. 4 [100]) and intersecting the second direction.
Regarding Claim 9, Chang discloses:
A lower surface of the buffer stack(Fig. 4 [141/130]) is higher than a lower surface of the first conductive contact(Fig. 4 [146]).
Regarding Claim 16, Chang discloses:
A semiconductor device(Fig. 3-5) comprising:
Active patterns(Fig. 3 [ACT]) on a substrate(Fig. 4 [100]);
An isolation pattern(Fig. 4 [105]) on the substrate(Fig. 4 [100]), the isolation pattern(Fig. 4 [105]) covering sidewalls of the active patterns(Fig. 3 [ACT]);
Gate structures(Fig. 5 [110]) spaced apart from each other in a second direction parallel to an upper surface of the substrate(Fig. 5 [100]), each of the gate structures(Fig. 5 [11]) extending through the active patterns(Fig. 3 [ACT]) and an upper portion of the isolation pattern(Fig. 5 [105]) in a first direction parallel to the upper surface of the substrate(Fig. 5 [100]) and perpendicular to the second direction;
First conductive contacts(Fig. 4 [146]) on central portions of the active patterns(Fig. 3 [ACT]), respectively ;
Second conductive contacts(Fig. 4 [120]) on end portions of the active patterns(Fig. 3 [ACT]), respectively ;
Buffer stacks(Fig. 4 [130/141]) on the active patterns(Fig. 3 [ACT]) and the isolation pattern(Fig. 4 [105]), the buffer stacks(Fig. 4 [130/141]) being disposed between the second conductive contacts(Fig. 4 [120]);
Bit line structures(Fig. 4 [140]) spaced apart from each other in the first direction, each of the bit line structures(Fig. 4 [140]) extending in the second direction on the first conductive contacts(Fig. 4 [146]) and the buffer stacks(Fig. 4 [130/141]);
Spacer structures(Fig. 4 [150/160SP]) on sidewalls in the first direction of the bit line structures(Fig. 4 [140]), the first conductive contacts(Fig. 4 [146]) and the buffer stacks(Fig. 4 [130/141]), each of the spacer structures(Fig. 4 [150/160SP]) including a first spacer(Fig. 4 [151]), a second spacer(Fig. 4 [153/152]), an etch stop pattern(Fig. 4 [154]) and a third spacer(Fig. 4 [160SP]) sequentially stacked in the first direction;
Landing pads(Fig. 4 [160]) on the second conductive contacts(Fig. 4 [120]), respectively; and
Capacitors(Fig. 4 [190]) on the second conductive contacts(Fig. 4 [120]), respectively,
wherein a lowermost surface of the first spacer(Fig. 4 [151]) is lower than a lowermost surface of the second spacer(Fig. 4 [152/153]), and lower surfaces of the etch stop pattern(Fig. 4 [154]) and third spacer(Fig. 4 [160SP]) are higher than the lowermost surface of the second spacer(Fig. 4 [152/153]).
Regarding Claim 17, Chang further discloses:
Fence patterns(Fig. 5 [170]) on the active patterns(Fig. 3 [ACT]) and the isolation patterns(Fig. 5 [105]), the fence patterns(Fig. 5 [170]) contacting a sidewall in the second direction of the second conductive contacts(Fig. 5 [120]).
Regarding Claim 18, Chang further discloses:
Filling patterns(Fig. 5 [113]) between a portion of the isolation pattern(Fig. 5 [105]) and the fence patterns(Fig. 5 [170]), the portion of the isolation pattern(Fig. 5 [105]) being adjacent to the central portion of the active patterns(Fig. 3 [ACT]), and the filling patterns(Fig. 5 [113]) covering lower sidewalls of the first conductive contacts(Fig. 4 [146], See Fig. 6 [146]),
Wherein upper surfaces of the central portion of each of the active patterns(Fig. 3 [ACT]) is lower than the end portions of the active patterns(Fig. 3 [ACT]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kim et al.(US 20210210493 A1, hereafter Kim).
Regarding Claim 2,
Chang does not teach or disclose the lower surface of the etch stop pattern is coplanar with the lower surface of the third spacer.
In the same field of endeavor, Kim discloses an etch stop pattern(Fig. 11A [156]) with a lower surface coplanar with a lower surface of a third spacer(Fig. 11A [158]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Chang along the lines of Kim. One might have been motivated to make a coplanar layer as to avoid a second etching step to place either layer at a lower level than the other, producing a device where the active area of the substrate can be protected from etchants in subsequent steps. Performing this modification would have generated a predictable result in a modified spacer in the device disclosed by Chang.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kim et al.(US 20220085028 A1, hereafter Kim 2)
Regarding Claim 3,
Chang does not teach or disclose the lowermost surface of the second spacer is coplanar with a lower surface of the second conductive contact.
In the same field of endeavor, Kim discloses a second contact(Fig. 2 [142]) with a lowermost surface coplanar with a lower surface of a second spacer(Fig. 2 [154]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Chang along the lines of Kim 2. One might have been motivated to make a coplanar layer as to avoid a second etching step to place either layer at a lower level than the other, producing a device with a spacer structure over a buried contact. Performing this modification would have generated a predictable result in a modified second contact in the device disclosed by Chang.
Claim(s) 7, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Lee et al.(US 20150061134 A1, hereafter Lee).
Regarding Claim 7,
Chang does not teach or disclose lowermost and uppermost surfaces of the fence pattern are coplanar with lowermost and uppermost surfaces of the second conductive contact, respectively.
In the same field of endeavor, Lee discloses a fence pattern(Fig. 3B [117]) and a second conductive contact(Fig. 3B [118]) which have coplanar lower and uppermost surfaces.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Chang along the lines of Lee. One might have been generate fence and contact patterns with flat surfaces, as to simplify the manufacturing process. Producing this device would generate a predictable result in the creation of Chang’s device with a modified second contact and fence structure.
Regarding Claim 19,
Chang discloses each of the second conductive contacts(Fig. 4/5 [120]) includes a lower portion(Fig. 5 See figure below) and an upper portion(Fig. 5 See figure below) arranged along a vertical direction perpendicular to the upper surface of the substrate(Fig. 4 [100]), the lower and upper portions having different widths in the first horizontal direction from one another;
Each of the fence patterns(Fig. 5 [170]) includes a lower portion(Fig. 5 See figure below) and an upper portion(Fig. 5 See figure below) arranged along the vertical direction, the lower and upper portions having different widths in the first horizontal direction from one another.
Chang does not teach or disclose lowermost and uppermost surfaces of the fence pattern are coplanar with lowermost and uppermost surfaces of the second conductive contact, respectively.
In the same field of endeavor, Lee discloses a fence pattern(Fig. 3B [117]) and a second conductive contact(Fig. 3B [118]) which have coplanar lower and uppermost surfaces.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Chang along the lines of Lee. One might have been generate fence and contact patterns with flat surfaces, as to simplify the manufacturing process. Producing this device would generate a predictable result in the creation of Chang’s device with a modified second contact and fence structure.
Regarding Claim 20, Chang further discloses:
Lower surfaces of the etch stop patterns(Fig. 4 [154]) and lower surfaces of the third spaces(Fig. 4 [160SP]) are coplanar with upper surfaces of the lower portions of the second conductive contacts(Fig. 4 [120]).
Claim(s) 10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kim et al.(US 20210296237 A1, hereafter Kim 3).
Regarding Claim 10,
Chang discloses a buffer stack(Fig. 4 [141/130]) including a first buffer(Fig. 4 [131]), a second buffer(Fig. 4 [132]) and a third buffer(Fig. 4 [141]) sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate(Fig. 4 [100]), and
The first spacer(Fig. 4 [151]) is disposed on an upper surface of the first buffer(Fig. 4 [141]).
Chang does not teach or disclose the first spacer as contacting each of opposite sidewalls in the first direction of the second and third buffers.
In the same field of endeavor, Kim 3 discloses a first spacer(Fig. 2 [321]) contacting each of the sidewalls of second and third buffers(Fig. 2 [330/332]).
It would have been obvious to one of ordinary skill in the art at the time the application hand was filed to modify the device disclosed by Chang along the lines of Kim 3. One might have been motivated to form a buffer layer as multiple layers such that the limitations of claim 10 are satisfied to better insulate the conductive structure of the bitline from other components, or to provide better structural stability to the device. Performing this modification would have generated a predictable result in the creation of Chang’s device with a modified buffer layer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Kim 3, further in view of Lim et al.(US 20220077152 A1, hereafter Lim).
Regarding Claim 11,
Neither Chang nor Kim 3 teach or disclose the second spacer contacts a sidewall of the first spacer and a sidewall of the first buffer in the first direction.
In the same field of endeavor, Lim discloses a second spacer(Fig. 25 [675]) contacting a sidewall of the first spacer(Fig. 25 [645]) and a sidewall of the first buffer(Fig. 25 [495]) in the first direction.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Chang along the lines of Lim. One might have been motivated to provide a second spacer covering a sidewall of the first buffer layer to accommodate the shape of the buffer layer, which can contain a series of layers of different thicknesses, requiring different spacers to avoid forming gaps in the structure. Performing this modification would have generated a predictable result in the creation of Chang’s device with a modified spacer structure.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Kim 3, further in view of Kim.
Regarding Claim 12,
Neither Chang nor Kim 3 teach or disclose a mold between the substrate and the buffer stack, wherein the etch stop pattern contacts a sidewall of the second spacer and a sidewall of the mold in the first direction.
In the same field of endeavor, Kim discloses a mold pattern(Fig. 11A [112]) between the substrate(Fig. 11A [110]) and the buffer stack(Fig. 11A [114]), wherein the etch stop pattern(Fig. 11A [156]) contacts a sidewall of the second spacer(Fig. 11A [AS]) and a sidewall of the mold(Fig. 11A [112]) in the first direction.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Chang along the lines of Kim. One might have been motivated to provide a mold layer beneath a buffer layer in order to better insulate the bit line structure from the substrate. Performing this modification would have generated a predictable result in the creation of Chang’s device with an additional mold layer below a buffer stack.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al.(US 20210082799 A1) discloses a buried contact with a bottom surface roughly at the same vertical level as a spacer. Kim et al.(US 20200395363 A1) discloses a plurality of spacer layers and buffer layers.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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