DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 15-16 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the implementing multi-level resistance includes, in response to the applied voltage having a first polarity, maintaining the first resistance as constant, and varying the second resistance based on variances in a magnitude of the voltage having the first polarity. And, wherein the implementing multi-level resistance includes, in response to the applied voltage having a second polarity, varying the first resistance and the second resistance based on variances in a magnitude of the voltage having the second polarity.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-6 and 10 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20210375360 to Gong et al. (“Gong”).
As to claim 1, Gong teaches A memory device (As found in at least the Abstract) comprising: a first electrode (As found in at least FIG. 2: either 114 or 102); a second electrode spaced apart from the first electrode (As found in at least FIG. 2: either 102 or 114); a self-selecting memory layer between the first and second electrodes, the self-selecting memory layer comprising a chalcogenide-based material, having ovonic threshold switching characteristics (As found in at least FIG. 2: 106; as found in at least [0028]: 106 is chalcogenide-based ovonic threshold switch (OTS)), and having a threshold voltage variable based on a polarity and a magnitude of a voltage applied to the self-selecting memory layer (As found in at least [0032]); and a memory layer between the second electrode and the self-selecting memory layer (As found in at least FIG. 2: 110), the memory layer having variable resistance characteristics based on a voltage applied to the memory layer (As found in at least [0031]: 106 is a PCM cell; also, see at least [0033]).
As to claim 5, Gong teaches wherein the memory device is configured such that multi-level resistance states are implemented by varying a polarity and a magnitude of a voltage applied between the first and second electrodes (As found in at least [0007], [0034], etc.).
As to claim 6, Gong teaches wherein the self-selecting memory layer comprises a chalcogen element comprising at least one of Se, Te, and S, and at least one of Ge, As, and Sb (As found in at least [0032]: 106 includes chalcogenide including at least Te, Se, Ge, etc.).
A to claim 10, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 7-9, 11-14 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210375360 to Gong et al. (“Gong”) in view of WO 2023200767 A1 to Grobis et al. (“Grobis”).
As to claim 2, at least Grobis teaches wherein the memory layer comprises at least one magnetic memory layer having variable resistance characteristics, variable with a magnetic field based on the voltage applied thereto (As found in at least FIG. 11A: MRAM 1112; also see at least [0003], [0048], etc.)
Gong and Grobis are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having magnetic memory elements.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Gong as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Grobis also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: the teachings of Grobis include an MRAM element stacked upon a OTS element, as found in at least FIG. 11A; both elements are responsive to voltages applied thereto, providing plurality of possible memory states.
Therefore, it would have been obvious to combine Gong with Grobis to make the above modification.
As to claim 3, Grobis teaches wherein the self-selecting memory layer and the at least one magnetic memory layer are electrically connected in series to each other (As found in at least FIG. 11A: self-selecting 1119 and magnetic memory 1112 in series).
As to claim 4, Grobis teaches wherein the at least one magnetic memory layer is included in a plurality of magnetic memory layers connected in series to each other (As found in at least FIG. 11A: layer 1111 included in a plurality of layers in series).
As to claim 7, Grobis teaches wherein the memory layer comprises a pinned layer, a free layer spaced apart from the pinned layer, and a tunnel barrier layer between the pinned layer and the free layer (As found in at least FIG. 11A; free layer 1111, pinned layer 1115 and tunnel layer 1113).
As to claim 8, Grobis teaches wherein the pinned layer and the free layer each comprises a ferromagnetic metal material having magnetism, and the tunnel barrier layer comprises a crystalline metal oxide (tunnel layer 1014 in FIG. 10A includes metal oxide MgO; while free layer 1010 and pinned layer 1012 include ferroelectric layers, as found in at least [0081]).
As to claim 9, Grobis teaches a third electrode between the self-selecting memory layer and the memory layer (As found in at least FIG. 11A: third electrode 1110 between memory layer 1112 and self-selecting layer 1109).
As to claim 11, see rejection to at least claim 3.
As to claim 12, see rejection to at least claim 4.
As to claim 13, see rejection to at least claim 5.
As to claim 14, at least Grobis teaches wherein a number of levels of the second resistance is greater than a number of the plurality of magnetic memory layers (As found in at least FIG. 11A, the number of magnetic layers in 1112 is two (2); while Gong teaches the number of levels of the second resistance 110 is four (4), as found in at least FIG. 4).
As to claim 17, see rejection to at least claim(s) 1-2; while at least Gong teaches: a plurality of bit lines; a plurality of word lines crossing the plurality of bit lines; and a plurality of memory cells at positions at which the plurality of bit lines and the plurality of word lines cross each other (As found in at least FIGS. 2-3).
As to claim 18, see rejection to at least claim 3.
As to claim 19, see rejection to at least claim 5.
As to claim 20, at least Grobis teaches wherein the plurality of bit lines and the plurality of word lines are in a multi-layer structure in which the plurality of bit lines and the plurality of word lines are alternately arranged in a vertical direction, and the plurality of memory cells are on upper and lower sides of each of the plurality of bit lines such that corresponding pairs of the plurality of memory cells are symmetrical with respect to a corresponding one of the plurality of bit lines (As found in at leas FIGS. 7C-7D).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights