DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and further in view of Walter (US Publication No. 20160156179).
Regarding claim 1, Kuranuki discloses a control unit (i.e., CU; see for example fig. 4 as shown below, para. [0049]- [0078]) comprising: a plurality of controllers (32, 12s) configured to control a load (E1-En), the plurality of controllers (32, 12s) being connected to respective circuit arrangements (X, Y, Z), the respective circuit arrangements (X, Y, Z) being defined as systems (i.e., X = Pack Detector System; Y = Battery Pack System; Z = Battery Pack System); an intersystem communication circuit (15s-16s, 35-36) connecting one of the systems (i.e., X = Pack Detector System; Y = Battery Pack System; Z = Battery Pack System) to another of the systems (i.e., X = Pack Detector System; Y = Battery Pack System; Z = Battery Pack System); an internal power supply circuit (Tp-Tn) being included in each of the systems (i.e., X = Pack Detector System; Y = Battery Pack System; Z = Battery Pack System), the internal power supply circuit (Tp- Tn) configured to supply electric power (i.e., such as battery pack 10 includes battery module 11 and battery controller 12. Battery module 11 is connected on a power line internally connecting positive electrode terminal Tp and negative-electrode terminal Tm of battery pack 10; see para. [0050]) to the intersystem communication circuit (15s-16s, 35-36) and a corresponding one (i.e., internal power line feeds each one of 32, 12, and 12) of the plurality of controllers (32, 12s); and a protection circuit (13-14, 17-18, RYp) configured to cut off (i.e., via RYp) an internal power supply line (PL) between the internal power supply circuit (Tp-Tn) and the intersystem communication circuit (15s-16s, 35-36) or limit supply of the electric power (i.e., via SS; seizing signal) to the intersystem communication circuit (15s-16s, 35-36), in response to an occurrence (i.e., such as abnormality occurs; see para. [0060]) of an overvoltage abnormality (i.e., such as overvoltage abnormality; see para. [0060]) in which an output voltage (i.e., such as based on the output voltage values; see para. [0060]) of the internal power supply circuit (Tp-Tn) is in an overvoltage state (i.e., such as overvoltage state; see para. [0060]).
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Kuranuki does not explicitly disclose wherein the overvoltage state of the one of the systems being determined based on a ground of the another of the systems, and the overvoltage state of the another of the systems being determined based on a ground of the one of the systems.
Koseki discloses an electronic control unit (i.e., such as EPS control ECU 14; see for example fig. 4, para. [0060]- [0070]); wherein the overvoltage state (i.e., such as overvoltage state as the voltage is high and exceeds a predetermined range; for instance, the first microcomputer 42a may determine that first GND connector 34a in the same system is in the abnormal state based on a current value obtained when the frequency that a voltage determined by first current-voltage conversion element 41a exceeds a predetermined value, or the frequency that the voltage is out of a predetermined range, is high, and second microcomputer 42b may determine that second GND connector 34b in the same system is in the abnormal state based on a current value obtained when the frequency that a voltage determined by second current-voltage conversion element 41b exceeds a predetermined value, or the frequency that the voltage is out of a predetermined range, is high. For the determination, the duration time may be measured or a count value of a counter may be used, and the connector rating should be considered, to prevent a burn or damage from occurring before performing the abnormality determination; see for example fig. 4, para. [0060]- [0070]) of the one of the systems (i.e., such as one of the systems A or B; see for example fig. 4, para. [0060]- [0070]) being determined (i.e., such as being determined; for instance, the determination of the abnormal state is not limited to be based on the direction of a current flowing through first and second current-voltage conversion elements 41a, 41b, but may be performed by various methods. For example, first microcomputer 42a may determine that first GND connector 34a in the same system is in the abnormal state when a current value obtained based on a voltage determined by first current-voltage conversion element 41a exceeds a predetermined value, or exceeds a predetermined range, and second microcomputer 42b may determine that second GND connector 34b in the same system is in the abnormal state when a current value obtained based on a voltage determined by second current-voltage conversion element 41b exceeds a predetermined value, or exceeds a predetermined range; see for example fig. 4, para. [0060]- [0070]) based on a ground (i.e., such as first GND connector 34a, or second GND connector 34b; see for example fig. 4, para. [0060]- [0070]) of the another of the systems (i.e., such as another of the systems B or A; see for example fig. 4, para. [0060]- [0070]), and the overvoltage state (i.e., such as overvoltage state as the voltage is high and exceeds a predetermined range; for instance, the first microcomputer 42a may determine that first GND connector 34a in the same system is in the abnormal state based on a current value obtained when the frequency that a voltage determined by first current-voltage conversion element 41a exceeds a predetermined value, or the frequency that the voltage is out of a predetermined range, is high, and second microcomputer 42b may determine that second GND connector 34b in the same system is in the abnormal state based on a current value obtained when the frequency that a voltage determined by second current-voltage conversion element 41b exceeds a predetermined value, or the frequency that the voltage is out of a predetermined range, is high. For the determination, the duration time may be measured or a count value of a counter may be used, and the connector rating should be considered, to prevent a burn or damage from occurring before performing the abnormality determination; see for example fig. 4, para. [0060]- [0070]) of the one of the systems (i.e., such as one of the systems A or B; see for example fig. 4, para. [0060]- [0070]) of the another of the systems (i.e., such as another of the systems B or A; see for example fig. 4, para. [0060]- [0070]) being determined (i.e., such as being determined; for instance, the determination of the abnormal state is not limited to be based on the direction of a current flowing through first and second current-voltage conversion elements 41a, 41b, but may be performed by various methods. For example, first microcomputer 42a may determine that first GND connector 34a in the same system is in the abnormal state when a current value obtained based on a voltage determined by first current-voltage conversion element 41a exceeds a predetermined value, or exceeds a predetermined range, and second microcomputer 42b may determine that second GND connector 34b in the same system is in the abnormal state when a current value obtained based on a voltage determined by second current-voltage conversion element 41b exceeds a predetermined value, or exceeds a predetermined range; see for example fig. 4, para. [0060]- [0070]) based on a ground (i.e., such as second GND connector 34b, or first GND connector 34a; see for example fig. 4, para. [0060]- [0070]) of the one of the systems (i.e., such as one of the systems A or B; see for example fig. 4, para. [0060]- [0070]) (i.e., first GND connector 34a corresponds to system A; similarly, second GND connector 34b corresponds to system B; see for example fig. 4, para. [0060]- [0070]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the multiple ground scheme in Kuranuki, as taught by Koseki, as it provides the advantage of optimizing the circuit design towards minimizing noise interference and ensuring safety against high-power fault currents.
Neither Kuranuki nor Koseki explicitly discloses wherein the ground of the one of the systems and the ground of the another of the systems is electrically isolated from each other.
Walter discloses an overvoltage protection circuit (i.e., see for example fig. 1, para. [0043]- [0066]); wherein the ground of the one of the systems (i.e., such as the ground of the one of the systems G1; see for example fig. 1, para. [0043]- [0066]) and the ground of the another of the systems (i.e., such as ground of the another of the systems G2; see for example fig. 1, para. [0043]- [0066]) are electrically isolated (i.e., such as electrically isolated as G1 and G2 are galvanically separated ground lines; see for example fig. 1, para. [0043]- [0066]) from each other (i.e., such as ground line G1 is galvanically separated from ground line G2; see for example fig. 1, para. [0043]- [0066]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the separated ground lines scheme in Kuranuki, as taught by Walter, as it provides the advantage of optimizing the circuit design towards blocking electrical noise, preventing stray current loops, and protecting sensitive devices.
Regarding claim 2, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Walter further discloses the overvoltage protection circuit (i.e., see for example fig. 1, para. [0043]- [0066]); wherein one of the systems (i.e., such as one of the systems T1; see for example fig. 1, para. [0043]- [0066]) is a first system (i.e., such as first system T1; see for example fig. 1, para. [0043]- [0066]) including a first ground (i.e., such as first ground G1; see for example fig. 1, para. [0043]- [0066]), another of the systems (i.e., such as another of the systems T2; see for example fig. 1, para. [0043]- [0066]) is a second system (i.e., such as second system T2; see for example fig. 1, para. [0043]- [0066]) including a second ground (i.e., such as second ground G2; see for example fig. 1, para. [0043]- [0066]) that is electrically isolated (i.e., such as electrically isolated as G1 and G2 are galvanically separated ground lines; see for example fig. 1, para. [0043]- [0066]) from the first ground (i.e., such as first ground G1; see for example fig. 1, para. [0043]- [0066]), the first system (i.e., such as first system T1; see for example fig. 1, para. [0043]- [0066]) and the second system (i.e., such as second system T2; see for example fig. 1, para. [0043]- [0066]) share a common ground (i.e., such as common ground MB; see for example fig. 1, para. [0043]- [0066]) that is located outside (i.e., such as MB is located outside MT) the control unit (i.e., such as the control unit MT; see for example fig. 1, para. [0043]- [0066]), the control unit (i.e., such as the control unit MT; see for example fig. 1, para. [0043]- [0066]) further comprises a third ground (i.e., such as third ground K; see for example fig. 1, para. [0043]- [0066]) that is isolated (i.e., such as ground line K is galvanically separated/isolated from G1 and G2; see for example fig. 1, para. [0043]- [0066]) from the first system (i.e., such as first system T1; see for example fig. 1, para. [0043]- [0066]) and the second system (i.e., such as second system T2; see for example fig. 1, para. [0043]- [0066]), the third ground (i.e., such as third ground K; see for example fig. 1, para. [0043]- [0066]) being connected (i.e., such as K being connected MB via KL1; see for example fig. 1, para. [0043]- [0066]) to the common ground (i.e., such as common ground MB; see for example fig. 1, para. [0043]- [0066]), and the overvoltage state (i.e., such as the overvoltage state of circuit 1 based on KL1; see for example fig. 1, para. [0043]- [0066]) of the first system (i.e., such as first system T1; see for example fig. 1, para. [0043]- [0066]) and the overvoltage state (i.e., such as the overvoltage state of circuit 1 based on KL2; see for example fig. 1, para. [0043]- [0066]) of the second system (i.e., such as second system T2; see for example fig. 1, para. [0043]- [0066]) are determined (i.e., such as determined; for instance, in order to check whether the ground differential voltage reaches the threshold value, overvoltage protection circuit 1 includes comparator circuit OP, which includes a comparator component 20 (for example, an operational amplifier). On the input side, the comparator component is connected via KL1 to the reference ground potential of the engine block, and via KL2 to the reference ground potential of the chassis, and compares the ground differential voltage to the threshold value. As long as ground strap MB establishes a galvanic connection between engine block M and the chassis, the two ground potentials are essentially equal, and the ground differential voltage is thus essentially zero. However, if the galvanic connection is impaired or damaged, the ground differential voltage increases; see for example fig. 1, para. [0043]- [0066]) based on the third ground (i.e., such as third ground K; see for example fig. 1, para. [0043]- [0066]). And, for the rest of the limitations/features in claim 2 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Regarding claim 8, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Kuranuki further discloses the control unit (i.e., CU; see for example fig. 4 as shown above, para. [0049]- [0078]); wherein the protection circuit (13-14, 17-18, RYp) includes: an overvoltage detection circuit (i.e., 13 monitor the current via 17 and monitor the voltage via 14) configured to monitor the output voltage (i.e., 13 monitor the current via 17 and monitor the voltage via 14 ); and a cutoff relay (RYp) being connected to the internal power supply line (PL), the cutoff relay (RYp) configured to be turned off (OFF/OPEN) in a case (i.e., such as when overvoltage, undervoltage, overcurrent, high-temperature abnormality, or low-temperature abnormality occurs, processor 13 turns off power relay RYp to protect the plurality of cells El to En; see para. [0060]) where the overvoltage detection circuit (i.e., 13 monitor the current via 17 and monitor the voltage via 14) detects (i.e., 13 monitor the current via 17 and monitor the voltage via 14) that the output voltage (i.e., such as based on the output voltage values; see para. [0060]) is in the overvoltage state (i.e., such as overvoltage state; see para. [0060]).
Regarding claim 9, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Koseki further discloses the electronic control unit (i.e., such as EPS control ECU 14; see for example fig. 4, para. [0060]- [0070]); wherein the load (i.e., such as load 13; see for example fig. 4, para. [0060]- [0070]) is a motor (i.e., such as electric motor 13; see for example fig. 4, para. [0060]- [0070]) or a motor generator.
Regarding claim 13, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Koseki further discloses the electronic control unit (i.e., such as EPS control ECU 14; see for example fig. 4, para. [0060]- [0070]); wherein the protection circuit (i.e., such as the protection circuit 32a, 32b; see for example fig. 4, para. [0060]- [0070]) and the internal power supply line (i.e., such as the internal power supply line 44a, 44b; see for example fig. 4, para. [0060]- [0070]) are included in each of the systems (i.e., such as in each of the systems A/31a, B/31b; see for example fig. 4, para. [0060]- [0070]), the protection circuit (i.e., such as the protection circuit 32a, 32b; see for example fig. 4, para. [0060]- [0070]) includes an overvoltage detection circuit (i.e., such as overvoltage detection circuit 45a, 45b; see for example fig. 4, para. [0060]- [0070]) and an overvoltage threshold generation circuit (i.e., such as overvoltage threshold generation circuit 41a, 41b; see for example fig. 4, para. [0060]- [0070]), the overvoltage threshold generation circuit (i.e., such as overvoltage threshold generation circuit 41a; see for example fig. 4, para. [0060]- [0070]) in the one of the systems (i.e., the one of the systems A/31a; see for example fig. 4, para. [0060]- [0070]) is configured to generate (i.e., such as configured to generate as to determine whether 1st-GND/34a is in the open state or in the normal state; see for example fig. 4, para. [0060]- [0070]) a first overvoltage threshold value (i.e., such as first overvoltage threshold value as 1st-GND/34a is in the open state; see for example fig. 4, para. [0060]- [0070]) with reference (i.e., such as with reference as comparing 34a with 34b because 42a and 42b are communicating with each other; see for example fig. 4, para. [0060]- [0070]) to the ground (i.e., such as the ground 2nd-GND/34b; see for example fig. 4, para. [0060]- [0070]) of the another of the systems (i.e., such as the another of the systems B/31b; see for example fig. 4, para. [0060]- [0070]), the overvoltage detection circuit (i.e., such as overvoltage detection circuit 45a; see for example fig. 4, para. [0060]- [0070]) in the one of the systems (i.e., the one of the systems A/31a; see for example fig. 4, para. [0060]- [0070]) is configured to detect (i.e., such as 45a is configured to detect via terminals DO and AD; see for example fig. 4, para. [0060]- [0070]) the overvoltage state (i.e., such as the overvoltage state as the voltage in line 36a exceeds a predetermined value; see for example fig. 4, para. [0060]- [0070]) of the one of the systems (i.e., the one of the systems A/31a; see for example fig. 4, para. [0060]- [0070]) based on a comparison result (i.e., such as comparison result by 42a; see for example fig. 4, para. [0060]- [0070]) between the first overvoltage threshold value (i.e., such as first overvoltage threshold value as 1st-GND/34a is in the open state; see for example fig. 4, para. [0060]- [0070]) and a voltage (i.e., such as voltage Va; see for example fig. 4, para. [0060]- [0070]) of the internal power supply line (i.e., such as the internal power supply line 44a; see for example fig. 4, para. [0060]- [0070]) in the one of the systems (i.e., the one of the systems A/31a; see for example fig. 4, para. [0060]- [0070]), the overvoltage threshold generation circuit (i.e., such as overvoltage threshold generation circuit 41b; see for example fig. 4, para. [0060]- [0070]) in the another of the systems (i.e., such as the another of the systems B/31b; see for example fig. 4, para. [0060]- [0070]) is configured to generate (i.e., such as configured to generate as to determine whether 2nd-GND/34b is in the open state or in the normal state; see for example fig. 4, para. [0060]- [0070]) a second overvoltage threshold value (i.e., such as second overvoltage threshold value as 2nd-GND/34b is in the open state; see for example fig. 4, para. [0060]- [0070]) with reference (i.e., such as with reference as comparing 34b with 34a because 42b and 42a are communicating with each other; see for example fig. 4, para. [0060]- [0070]) to the ground (i.e., such as the ground 1st-GND/34a; see for example fig. 4, para. [0060]- [0070]) of the one of the systems (i.e., the one of the systems A/31a; see for example fig. 4, para. [0060]- [0070]), and the overvoltage detection circuit (i.e., such as overvoltage detection circuit 45b; see for example fig. 4, para. [0060]- [0070]) in the another of the systems (i.e., such as the another of the systems B/31b; see for example fig. 4, para. [0060]- [0070]) is configured to detect (i.e., such as 45b is configured to detect via terminals DO and AD; see for example fig. 4, para. [0060]- [0070]) the overvoltage state (i.e., such as the overvoltage state as the voltage in line 36b exceeds a predetermined value; see for example fig. 4, para. [0060]- [0070]) of the another of the systems (i.e., such as the another of the systems B/31b; see for example fig. 4, para. [0060]- [0070]) based on a comparison result (i.e., such as comparison result by 42b; see for example fig. 4, para. [0060]- [0070]) between the second overvoltage threshold value (i.e., such as second overvoltage threshold value as 2nd-GND/34b is in the open state; see for example fig. 4, para. [0060]- [0070]) and a voltage (i.e., such as voltage Vb; see for example fig. 4, para. [0060]- [0070]) of the internal power supply line (i.e., such as the internal power supply line 44b; see for example fig. 4, para. [0060]- [0070]) in the another of the systems (i.e., such as the another of the systems B/31b; see for example fig. 4, para. [0060]- [0070]).
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and in view of Walter (US Publication No. 20160156179) and further in view of Moen (US Publication No. 20150372476).
Regarding claim 3, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Neither Kuranuki nor Koseki nor Walter explicitly discloses wherein the protection circuit includes: a fuse being connected to the internal power supply line; and a Zener diode being connected to a wiring, the wiring being connected between a ground and an end of the fuse, the end of the fuse being connected to the intersystem communication circuit.
Moen discloses a protective module for a power supply of a bus communication unit (i.e., see for example fig. 3 as shown below, para. [0059]- [0062]); wherein the protection circuit (310a-310c) includes: a fuse (i.e., 214; see for example fig, 2 as shown below, para, [0052]- [0058]) being connected to the internal power supply line (211); and a Zener diode (216) being connected to a wiring (W), the wiring (W) being connected between a ground (GND) and an end (n) of the fuse (214), the end (n) of the fuse (214) being connected to the intersystem communication circuit (213).
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Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ground scheme in Kuranuki, as taught by Moen, as it provides the advantage of optimizing the circuit design towards minimizing electromagnetic interference (EMI) and noise.
Regarding claim 7, Kuranuki in view of Koseki and in view of Walter and further in view of Moen and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter and the teachings of Kuranuki as modified by Moen have been discussed above as well.
Moen further discloses the protective module (i.e., see for example fig. 3 as shown above, para. [0059]- [0062]); wherein the protection circuit (310a-310c) includes: a switching element (i.e., 218; see for example fig. 2 as shown above, para. [0052]- [0058]) being connected to the internal power supply line (211); and a [the] Zener diode (216) being connected between the internal power supply line (211) and the ground (i.e., GND; Gr, Gs, Gt) of the another (i.e., systems R, S, T) of the systems (i.e., Gr is in R; Gs is in S; Gt is in T), and the switching element (218) is configured to be: turned on (ON) in a case (i.e., the normal case scenario which is the opposite of the overvoltage scenario; see para. [0054]) where the output voltage (i.e., such as the input diode 218 assures that the input terminal 211 is isolated from the output terminal 213 and the input/output terminal 212 if the voltage provided by the power supply unit 205 is too low; see para. [0054]) is in a normal state (i.e., the normal case scenario which is the opposite of the overvoltage scenario; see para. [0054]); and turned off (OFF) due to a current flow (i.e., such as the current flows will break and thereby isolate; see para. [0055]) toward the Zener diode (216) in a case (i.e., such as the input/output terminal 212 when the voltage provided by the power supply 205 is above a certain threshold; see para. [0054] where the output voltage (i.e., such as the input diode 218 assures that the input terminal 211 is isolated from the output terminal 213 and the input/output terminal 212 if the voltage provided by the power supply unit 205 is too low; see para. [0054]) is in the overvoltage state (i.e., such as the voltage over the input diode exceeds the diode forward voltage drop; see para. [0054]).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and in view of Walter (US Publication No. 20160156179) and in view of Moen (US Publication No. 20150372476) and further in view of Nassar et al (US Publication No. 20140268443).
Regarding claim 4, Kuranuki in view of Koseki and in view of Walter and further in view of Moen and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter and the teachings of Kuranuki as modified by Moen have been discussed above as well.
Neither Kuranuki nor Koseki nor Walter nor Moen explicitly discloses wherein the fuse is a chip current fuse or a chip resistor, the chip current fuse is configured to be mounted on a board, and the chip resistor is configured to be disconnected at a voltage lower than a Zener voltage of the Zener diode.
Nassar discloses a protective apparatus (i.e., see for example fig. 2 as shown below, para. [0051]- [0085]); wherein the fuse (210) is a chip current fuse (i.e., such as an overcurrent protective fusible chip; see for example para. [0056]) or a chip resistor (i.e., such as resistor chip; see for example para. [0167]), the chip current fuse (i.e., such as an overcurrent protective fusible chip; see for example para. [0056]) is configured to be mounted on a board (i.e., such as a board; see for example para. [0049]), and the chip resistor (i.e., such as resistor chip; see for example para. [0167]) is configured to be disconnected at a voltage (i.e., such as when in the voltage regulation state; see for example para. [0037]) lower (i.e., such as a reversible breakdown; see for example para. [0069]) than a Zener voltage (i.e., such as a Zener breakdown voltage; see for example [0037]) of the Zener diode (i.e., such as migration of metals across a PN junction of the Zener diode in response; see for example para. [0037]).
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Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the fuse-Zener chip in Kuranuki, as taught by Nassar, as it provides the advantage of optimizing the circuit design towards clamping voltage spikes and diverting excessive current.
Regarding claim 5, Kuranuki in view of Koseki and in view of Walter and in view of Moen and further in view of Nassar and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter and the teachings of Kuranuki as modified by Moen and the teachings of Kuranuki as modified by Nassar have been discussed above as well.
Nassar further discloses the protective apparatus (i.e., see for example fig. 2 as shown above, para. [0051]- [0085]); wherein the fuse (210) is a bonding wire (i.e., such as a wire bond fuse; see for example para. [0092]) inside an integrated circuit (i.e., such as IC chip 200; see for example [0092]) included in the internal power supply circuit (202), the bonding wire (i.e., such as a wire bond fuse; see for example para. [0092]) is connected to an output terminal (204) of the integrated circuit (200), and the output terminal (204) is connected to the intersystem communication circuit (i.e., 204; output terminal 204 can be connected to any load circuit such as the intersystem communication circuit).
Regarding claim 6, Kuranuki in view of Koseki and in view of Walter and in view of Moen and further in view of Nassar and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter and the teachings of Kuranuki as modified by Moen and the teachings of Kuranuki as modified by Nassar have been discussed above as well.
Nassar further discloses the protective apparatus (i.e., see for example fig. 2 as shown above, para. [0051]- [0085]); wherein the fuse (210) is a fuse pattern (i.e., such fuse wire bonds; see for example para. [0118]) included in a wiring pattern (i.e., such as and/or wire routing conductors as desired; see for example para. [0118]) on a [the] board, the wiring pattern (i.e., such as and/or wire routing conductors as desired; see for example para. [0118]) forms a current path (i.e., of course and with absolute certainty a conductive wire will conduct a current from source to load) connecting the internal power supply circuit (202) and the intersystem communication circuit (i.e., 204; output terminal 204 can be connected to any load circuit such as the intersystem communication circuit), and the fuse pattern (i.e., such as fuse wire bonds; see for example para. [0118]) is locally slimmer (i.e., such as is less than or equal to 1.5 times the size of the die, or can be an embedded thin-film metal fuse or polysilicon electronic fuse (e-fuse) structure; see for example para. [0120]) than another pattern (i.e., such as a chip-scale package (CSP) device; see for example para. [0116]) located in the wiring pattern (i.e., such as and/or wire routing conductors as desired; see for example para. [0118]) (i.e., such as wiring pattern is greater than 1.5 times the size of the die; see for example para. [0116]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and in view of Walter (US Publication No. 20160156179) and further in view of Allen et al (US Patent No. 3725613).
Regarding claim 10, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Neither Kuranuki nor Koseki nor Walter explicitly discloses wherein the protection circuit includes: a fuse at the internal power supply line; a Zener diode; and a diode, a cathode of the Zener diode is connected to a connection node between the fuse and the intersystem communication circuit, an anode of the diode is connected to an anode of the Zener diode, and a cathode of the diode is connected to the common ground, the ground of the one of the systems, or the ground of the another of the systems.
Allen discloses a protection apparatus (i.e., see for example fig. 2 as shown below, Col. 4 lines 57+); wherein the protection circuit (A) includes: a fuse (14) at the internal power supply line (16); a Zener diode (32); and a diode (33), a cathode (B) of the Zener diode (32) is connected to a connection node (D) between the fuse (14) and the intersystem communication circuit (C), an anode (E) of the diode (33) is connected to an anode (E) of the Zener diode (32), and a cathode (F) of the diode (33) is connected to the common ground (G), the ground (G) of the one of the systems (21, 20), or the ground of the another of the systems.
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Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ground scheme in Kuranuki, as taught by Allen, as it provides the advantage of optimizing the circuit design towards minimizing electromagnetic interference (EMI) and noise.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and in view of Walter (US Publication No. 20160156179) and further in view of Mertz et al (US Patent No. 5153802).
Regarding claim 11, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Neither Kuranuki nor Koseki nor Walter explicitly discloses wherein the protection circuit includes: a switching element at the internal power supply line; and a Zener diode connected between the internal power supply line and either the common ground or the ground of the another of the systems, wherein a cathode of the Zener diode is connected to a connection node between the internal power supply line circuit and the switching element, and an anode of the Zener diode is connected, through a resistor, to the common ground, the ground of the one of the systems, or the ground of the another of the systems.
Mertz discloses a static switch (i.e., see for example fig. 7 as shown below, Col. 6 lines 63+); wherein the protection circuit (13) includes: a switching element (BP) at the internal power supply line (V2); and a Zener diode (ZD) connected between the internal power supply line (V2) and either the common ground (GND) or the ground of the another of the systems, wherein a cathode (K) of the Zener diode (ZD) is connected to a connection node (N) between the internal power supply line circuit (V2) and the switching element (BP), and an anode (M) of the Zener diode (ZD) is connected, through a resistor (R12), to the common ground (GND), the ground (GND) of the one of the systems (A), or the ground of the another of the systems.
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Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ground scheme in Kuranuki, as taught by Mertz, as it provides the advantage of optimizing the circuit design towards minimizing electromagnetic interference (EMI) and noise.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kuranuki et al (US Publication No. 20230095740) in view of Koseki et al (US Publication No. 20210046973) and in view of Walter (US Publication No. 20160156179) and further in view of Marenski (US Publication No. 20180172740).
Regarding claim 12, Kuranuki in view of Koseki and further in view of Walter and the teachings of Kuranuki as modified by Koseki have been discussed above. Also, the teachings of Kuranuki as modified by Walter have been discussed above as well.
Neither Kuranuki nor Koseki nor Walter explicitly discloses wherein the internal power supply circuit in the one of the systems is connected to the ground of the another of the systems, and the internal power supply circuit in the another of the systems is connected to the ground of the one of the systems.
Marenski discloses an apparatus arrangement (i.e., see for example fig. 2, para. [0032]- [0051]); wherein the internal power supply circuit (i.e., such as the internal power supply circuit 30; see for example fig. 2, para. [0032]- [0051]) in the one of the systems (i.e., such as the one of the systems 21; see for example fig. 2, para. [0032]- [0051]) is connected (i.e., such as 30 is connected to 43 via 47; see for example fig. 2, para. [0032]- [0051]) to the ground (i.e., such as the ground GND/43; see for example fig. 2, Col. 2 lines 72+) of the another of the systems (i.e., such as the another of the systems 22; see for example fig. 2, Col. 2 lines 72+), and the internal power supply circuit (i.e., such as the internal power supply circuit 40; see for example fig. 2, para. [0032]- [0051]) in the another of the systems (i.e., such as the another of the systems 22; see for example fig. 2, Col. 2 lines 72+) is connected (i.e., such as 40 is connected to 33 via 48; see for example fig. 2, para. [0032]- [0051]) to the ground (i.e., such as the ground GND/33; see for example fig. 2, Col. 2 lines 72+) of the one of the systems (i.e., such as the one of the systems 21; see for example fig. 2, para. [0032]- [0051]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the butterfly connection scheme for the ground lines in Kuranuki, as taught by Marenski, as it provides the advantage of optimizing the circuit design towards it preventing ground loops, reducing noise coupling, and eliminating ground offsets.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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