Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 08/03/2026. Currently, claims 1-24 are pending in the application. Claims 12-14 and 19-24 are withdrawn from Consideration.
Election/Restrictions
Applicant's election with traverse of Group I and Species IB (Figure 2), claims 1-11 and 15-18, in the reply filed on 08/03/2026 is acknowledged.
The first traversal is on the ground(s) that the examination of all of claims 1-24 would not present an undue burden on the Examiner, and respectfully request reconsideration and withdrawal of the Restriction Requirement.
This is not found persuasive and the Examiner has already established burden (as defined in M.P.E.P. 808.02) in the restriction requirement dated 06/04/2026. There is a search and/or examination burden for the patentably distinct species or device/method claims, wherein they require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one invention would not likely be applicable to another; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C 101 and/or 35 U.S.C 112, first paragraph. Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WU et al (US 20210210447 A1).
Regarding claim 1, Figure 12 of WU discloses a semiconductor structure, comprising:
an interconnect structure (100, [0028]) comprising a conductive pad (102, [0027]) located at a top of the interconnection structure;
a passivation layer (106, [0032]) disposed on the interconnection structure, wherein the passivation layer has a first opening to expose a portion of the conductive pad; and
a dielectric capping layer (105, [0033]) conformally formed on the passivation layer and extending into the first opening, wherein the dielectric capping layer has a second opening to expose the portion of the conductive pad (102).
Regarding claim 2, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, wherein a top surface of the dielectric capping layer (105) is a flat surface.
Regarding claim 3, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, wherein the first opening is aligned with the second opening, and the dielectric capping layer (105, [0033]) lines a first sidewall of the first opening and is in contact with the passivation layer (106) and the portion of the conductive pad exposed from the first opening.
Regarding claim 4, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 3, wherein in a direction substantially parallel to a top surface of the passivation layer (106), the first opening has a first dimension, and the second opening has a second dimension that is less than the first dimension.
Regarding claim 5, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, wherein a thickness of the dielectric capping layer is between about 25 Å and 50 μm ([0033]).
Regarding claim 6, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, wherein a first angle between a first side surface of the dielectric capping layer (105) in the first opening and away from the passivation layer (106) and a top surface of the conductive pad (102) is less than or equal to 95 degrees (based on Figure 12).
Regarding claim 7, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, further comprising; a photosensitive stress buffer layer (110, [0049]) conformally formed on the dielectric capping layer (105), wherein the photosensitive stress buffer layer has a third opening to expose the portion of the conductive pad (102).
Regarding claim 8, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 7, wherein the second opening (in 105) is aligned with the third opening (in 110).
Regarding claim 9, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 7, wherein the photosensitive stress buffer layer (110) lines a second sidewall of the second opening and is in contact with the dielectric capping layer (105) and a portion of the conductive pad exposed from the second opening.
Regarding claim 10, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 9, wherein in a direction substantially parallel to a top surface of the passivation layer (106), the second opening has a second dimension, and the third opening has a third dimension that is less than the second dimension (based on Figure).
Regarding claim 11, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 9, wherein a second angle between a second side surface of the photosensitive stress buffer layer (110) away from the dielectric capping layer (105) located in the second opening and a top surface of the conductive pad (102) is less than or equal to 95 degrees (based on Figure).
Regarding claim 15, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 1, wherein the interconnect structure (100) further comprises a first passivation layer (100f, [0028]) disposed underlying the conductive pad (102), wherein the passivation layer (106) is a second passivation layer covering the first passivation layer (100f).
Regarding claim 16, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 15, further comprising a conductive bump (109, [0027]) structure disposed on the second passivation layer, passing through the first opening and the second opening and connected to the conductive pad (102), wherein the dielectric capping layer (105) is interposed between the second passivation layer (106) and the conductive bump structure (109).
Regarding claim 17, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 16, wherein the conductive bump structure and the conductive pad comprise the same material (considering copper for both, [0029] and [0052]).
Regarding claim 18, Figure 12 of WU discloses that the semiconductor structure as claimed in claim 16, wherein the second passivation layer (106) and the dielectric capping layer (105) are formed of different materials ([0032]-[033]).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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