DETAILED ACTION
This action is responsive to the following communications: the Application filed April 17, 2024, and Response to Election / Restriction filed January 12, 2026.
Claims 1-20 are pending. Claims 10-20 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 17, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Berdan et al. (US 2022/0405057) in view of Yang et al. (US 12,524,207).
Regarding independent claim 1, Berdan et al. teach a method for improving linearity during multiply and accumulate (MAC) computations in an in memory computing (IMC) macro (e.g., para. 0027: … executes sum-of-product operation that multiplies a multi-bit input by a multi-bit weight and adds results of the multiplication …) comprising:
converting an input activation of analog input into binary pulses;
applying the binary pulses as a digital bitstream to the IMC macro for computation (e.g., para. 0029: … executed in a memory device by performing the arithmetic logic operation …; also para. 0036: … the input data Din …); and
determining output bits by performing charge-domain MAC computations on the binary pulses and weights stored in the IMC macro (e.g., para. 0029: … executed in a memory device by performing the arithmetic logic operation corresponding to a weight bit for an input bit in a bit-wise logical operation circuit arranged in the memory … also para. 0036: … the input data Din … and a weight vector W …); and
providing the output bits through a plurality of read bit lines (RBL) bits (e.g., FIG. 1: Vy to Dy, along with FIG. 8: Y, i.e., para. 0100: bit lines BL0 to BL(n-1)).
Berdan et al’ input data (e.g., FIG. 1: Din) does not explicitly disclose an analog input and converting into binary data.
However, analog input converting into digital data for a computing device is a well-known technology for a type of computing device for its purpose.
For support, of the above asserted facts, see for example, Yang’s FIG. 1: ADC, and accompanying disclosure.
Berdan and Yang are analogous art because they both are directed to computing operations with SRAM device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Berdan with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yang et al. to the teaching of Berdan et al. such that a logic operation system, as taught by Berdan et al., utilizes ADC, as taught by Yang et al., for the purpose of utilizing analog input and performing logic operation, thereby achieving high performance logic operations with analog input.
Regarding claim 2, Berdan et al. and Yang et al., as combined, teach the limitations of claim 1.
Berdan et al. further teach combining and weighting the plurality of RBL bits based on bit positions of the plurality of RBL bits (e.g., para. 0025: a bit position value of a weigh of multiple bits).
Regarding claim 3, Berdan et al. and Yang et al., as combined, teach the limitations of claim 1.
Berdan et al. further teach the IMC macro comprises: an array of capacitive bitcells having between six and twelve transistors inclusive (e.g., FIGS. 10-11).
Regarding claim 4, Berdan et al. and Yang et al., as combined, teach the limitations of claim 3.
Berdan et al. further teach charging the array of capacitive bitcells by applying the binary pulses to a static random access memory (SRAM) capacitor through a read word line (RWL) (FIGS. 10-11: WL).
Regarding claim 5, Berdan et al. and Yang et al., as combined, teach the limitations of claim 3.
Berdan et al. further the array of capacitive bitcells comprises: a 64x64 array of 9T1C SRAM with weights (e.g., para. 0119: a 9T1C type).
Berdan et al. do not explicitly disclose 64x64 array.
However, Yang et al. disclose 128x64 array (FIG. 1); and expanding the size of an array in a memory array such as 64x64 array is a well-known technology for a type of memory (e.g., SRAM) for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used a variety size of matrices structure because these conventional technology are well established in the art of the memory devices.
Regarding claim 6, Berdan et al. and Yang et al., as combined, teach the limitations of claim 1.
Berdan and Yang are silent with respect to creating the binary pulses using a delta-sigma modulator (DSM).
However, the claimed DSM in pulse generation is a well-known technology for a type of data processing for its purpose.
For support, of the above asserted facts, see for example, Greer, III (US 2017/0039926), FIG. 3 and accompanying disclosure, e.g., para. 0034: a delta-sigma modulator … binary scalars having a value of one or zero generated as output signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize DSM in pulse generation because these conventional technology are well established in the art of the memory devices.
Regarding claims 7-8, Berdan et al., Yang et al., as combined, teach the limitations of claim 6.
Berdan and Yang are silent with respect to reconfiguring the DSM to modify a binary pulse train; and dynamically reconfiguring the input activation by changing an oversampling ratio (OSR) of the DSM.
However, the claimed a binary pulse train and oversampling ratio of the DSM is a well-known technology for a type of data processing for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize DSM in pulse generation because these conventional technology are well established in the art of the memory devices.
Regarding claim 9, Berdan et al. and Yang et al., as combined, teach the limitations of claim 1.
Berdan et al. further teach the IMC macro comprises: an array of 9T1C SRAM bitcells (e.g., para. 0119: a 9T1C type).
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825