Prosecution Insights
Last updated: July 17, 2026
Application No. 18/638,429

SEMICONDUCTOR DIE WITH BURIED ELECTRICAL INTERCONNECTIONS

Non-Final OA
Filed
Apr 17, 2024
Priority
Dec 20, 2023 — IN 202341087415
Examiner
VU, DAVID
Art Unit
Tech Center
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
573 granted / 744 resolved
+17.0% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
16 currently pending
Career history
758
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
69.5%
+29.5% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
2.8%
-37.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 744 resolved cases

Prosecution Timeline

Apr 17, 2024
Application Filed
May 20, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684986
DISPLAY DEVICE
2y 9m to grant Granted Jul 14, 2026
Patent 12685040
GROUP-III ELEMENT NITRIDE SEMICONDUCTOR SUBSTRATE
2y 11m to grant Granted Jul 14, 2026
Patent 12672431
Display Substrate and Display Device
2y 7m to grant Granted Jun 30, 2026
Patent 12660395
ELECTRONIC DEVICE
2y 9m to grant Granted Jun 16, 2026
Patent 12660212
CAPACITOR STRUCTURE, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR STRUCTURE
2y 9m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.1%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 744 resolved cases by this examiner. Grant probability derived from career allowance rate.

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