DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the limitation “a width of the multiple vertical interconnect bars” in lines 2-3 is not clear because the bars can have different widths.
Regarding claim 9, the limitation “a height of the multiple vertical interconnect bars” in lines 1-2 is unclear, because interconnect bars can have a different height.
The claims are interpreted as the width and the height of one of these interconnect bars.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et. al., U. S. Pat. Pub. 2021/0288034, hereafter ‘34.
PNG
media_image1.png
501
806
media_image1.png
Greyscale
Regarding claim 1, ‘34 discloses (see annotated Fig. 1) an electronic package comprising: multiple staircased dies [12],[14],[16],[18], the multiple staircased dies including multiple contact ledges (Fig. 1, par. [0028]); multiple vertical wire [11],[13],[15],[17] bonds bonded to the multiple contact ledges (see Fig. 1); and a molding layer [40] (Fig. 1C) that encapsulates the multiple staircased dies and the multiple vertical wire bonds, wherein the multiple vertical wire bonds extend past a top surface and stand proud above the molding layer [40].
Regarding claim 2, ‘34 further discloses (par. [0019]) wherein the multiple staircased dies are memory dies.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et. al., U. S. Pat. Pub. 2025/0316635, hereafter Kim.
Regarding claim 1, Kim discloses (Fig. 1) an electronic package comprising: multiple staircased dies, the multiple staircased dies [100] including multiple contact ledges (areas of each die [100] where contacts [110] are located, see Fig. 1); multiple vertical wire [300] bonds bonded [300B] to the multiple contact ledges [110] (Fig. 5); and
a molding layer [410] that encapsulates the multiple staircased dies [100] and the multiple vertical wire bonds [300B], wherein (Fig. 16C,D) the multiple vertical wire bonds [300] extend past a top surface (of [410]) and stand proud above the molding layer [410].
Regarding claim 2, Kim further discloses wherein the multiple staircased dies are memory dies (par. [0033]).
Claims 6-11 (as best understood above) are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et. al., U. S. Pat. Pub. 2022/0254755, hereafter Zeng.
Regarding claim 6, Zeng discloses (Fig. 13) an electronic package comprising: multiple staircased dies [946],[1046], [1146], [1246], the multiple staircased dies including multiple contact ledges (die areas where contact pillars [916], [926], [1316], [1326] are attached); multiple vertical interconnect bars [502],[504],[506],[508] bonded to the multiple contact ledges; and
a molding layer [1180] (labeled in Fig. 11) that encapsulates the multiple staircased dies and the multiple vertical interconnect bars (see Fig. 13).
Regarding claim 7, Zeng further discloses (par. [0054], claim 11) wherein the multiple staircased dies are memory dies.
Regarding claim 8, Zeng further discloses (as best understood) wherein a height of the multiple vertical interconnect bars [502]-[508]extend from the multiple contact ledges (for die [1246]) to a top surface of the molding layer [1180], and a width of the multiple vertical interconnect bars [508] is less than a width of the multiple contact ledges (for die[1346], see Fig. 13.
Regarding claim 9, Zeng further discloses (as best understood, Fig. 13) wherein the multiple staircased dies include a first set of dies (on the left) that includes a first upper die [1246] attached to a first lower die [1346] , and a second set of dies (on the right) that includes a second upper die[1246] and a second lower die [1346], the first set of dies and the second set of dies being positioned so that the multiple vertical wire bonds [1316], [1346] are located at a first edge and a second edge on the electronic package (see Fig. 13).
Regarding claim 10, Zeng further discloses (Fig. 13) wherein the multiple staircased dies include a first set of dies that includes (to the left of [1305]) a first upper die [1046] attached to a first lower die [1146], and a second set of dies (to the right of [1305]) that includes a second upper die [1046] and a second lower die [1146], the first set of dies and the second set of dies being positioned so that the multiple vertical interconnect bars are located at a central location on the electronic package (near the line [1305]).
Regarding claim 11, Zeng further discloses (Fig. 13) wherein the multiple staircased dies include a first set of dies (left of [1305]) that includes a first upper die [1246] attached to a first lower die [1346], and a second set of dies (right of [1305]) that includes a second upper die [1246] and a second lower die [1346], the first set of dies and the second set of dies being positioned so that the multiple vertical interconnect bars [502], [504], [506],[508] are located at a first edge and a second edge on the electronic package (see Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et. al., U. S. Pat. Pub. 2021/0288034, hereafter ’34, in view of Dayringer et. al., U.S. Pat. 9,082,632, hereafter Dayringer.
Regarding claim 3, ’34 discloses everything as applied above. ’34 fails to explicitly disclose
wherein the multiple vertical wire bonds include a first region with a first pitch size and a second region with a second pitch size, the first pitch size being greater than the second pitch size.
However, Dayringer discloses (Fig 5A, 8) a first region with a first pitch size [570] and a second d region with a second pitch size [572], the first pitch size being greater than the second pitch size.
It would have been obvious to one of ordinary skill in the art to modify ’34 with the teachings of multiple pitch sizes of Dayringer to facilitate reliable and fast electrical connection. Modifying a size of a connector to provide a better quality connection is normally considered obvious in the art (MPEP, 2144.04.IV.A, and case law therein).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et. al., U. S. Pat. Pub. 2021/0288034, hereafter ’34, in view of Zeng et. al., U. S. Pat. Pub. 2022/0254755, hereafter Zeng.
Regarding claim 4, ’34 discloses everything as applied above. ’34 fails to explicitly disclose
wherein the multiple staircased dies include a first set of dies that includes a first upper die attached to a first lower die, and a second set of dies that includes a second upper die and a second lower die, the first set of dies and the second set of dies being positioned so that the multiple vertical wire bonds are located at a central location on the electronic package.
However, Zeng discloses (Fig. 13) wherein the multiple staircased dies include a first set of dies (left of [1305]) that includes a first upper die [1046] attached to a first lower die [1146], and a second set of dies (right of [1305]) that includes a second upper die [1046] and a second lower die [1146], the first set of dies and the second set of dies being positioned so that the multiple vertical wire bonds [916], [926] are located at a central location on the electronic package.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to arrange dies of ’34 so that multiple wire bonds are located in the center of the stacked package because rearranging connectors and parts is normally considered obvious in the art (MPEP, latest revision, 2144.04.VI.C), and an arrangement of stacked chips with the wires near center is well known for 3D NAND memory devices.
Regarding claim 5, ’34 discloses everything as applied above. ’34 fails to explicitly disclose wherein the multiple staircased dies include a first set of dies that includes a first upper die attached to a first lower die, and a second set of dies that includes a second upper die and a second lower die, the first set of dies and the second set of dies being positioned so that the multiple vertical wire bonds are located at a first edge and a second edge on the electronic package.
However, Zeng discloses (Fig. 13) wherein the multiple staircased dies include a first set of dies (on the left) that includes a first upper die [1246] attached to a first lower die [1346] , and a second set of dies (on the right) that includes a second upper die[1246] and a second lower die [1346], the first set of dies and the second set of dies being positioned so that the multiple vertical wire bonds [1316], [1346] are located at a first edge and a second edge on the electronic package (see Fig. 13).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to arrange dies of ‘34 so that multiple wire bonds are located in the center of the stacked package because rearranging connectors and parts is normally considered obvious in the art (MPEP, latest revision, 2144.04.VI.C), and an arrangement of stacked chips with the wires near the edges of the package is well known for 3D NAND memory devices.
Claims 12-13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et. al., U. S. Pat. Pub. 2022/0254755, hereafter Zeng, in view of Tanaka, U.S. Pat. Pub. 2023/0411357, hereafter Tanaka.
Regarding claim 12, Zeng discloses (Fig. 14) a package-on-package structure comprising: multiple staircased electronic packages including at least a first set of electronic packages (left), the first set of electronic packages including a first upper electronic package [1046] and a first lower electronic package [1146];
a vertical interconnect array bar [502], [504], [506], [508]; and
a molding layer [1180] (see Fig. 11) that encapsulates the multiple staircased electronic packages and the vertical interconnect array bar.
Zeng fails to explicitly disclose
one or more support structures, the one or more support structures including at least a first support structure located adjacent to the first lower electronic package and below the first upper electronic package;
the molding layer encapsulating the one or more support structures.
However, Tanaka discloses
one or more support structures [32], the one or more support structures including at least a first support structure located adjacent to the first lower electronic package [40] and below the first upper electronic package [50];
the molding layer [65] encapsulating the one or more support structures [32].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the package structure of Zeng with support structure of Tanaka to improve structural stability of the memory stack.
Regarding claim 13, Zeng in view of Tanaka discloses everything as applied above. Zeng further discloses (Fig. 13, par. [0020]) wherein the multiple staircased electronic packages each include multiple staircased dies, the multiple staircased dies being memory dies.
Regarding claim 17, Zeng in view of Tanaka discloses everything as applied above. Zeng further discloses (Fig. 13, left side) wherein the first upper electronic package and the first lower electronic package each include:
multiple staircased dies [1046], [1146], the multiple staircased dies including multiple contact ledges (the places where [916], [926] are connected);
multiple vertical interconnect bars [502], [504]bonded to the multiple contact ledges; and
a molding layer [1180] (Fig. 11) that encapsulates the multiple staircased dies and the multiple vertical interconnect bars (see Fig. 13).
Regarding claim 18, Zeng in view of Tanaka discloses everything as applied above. Zeng further discloses (Fig. 13, right side) further comprising a second set of electronic packages including a second upper electronic package [1046] and a second lower electronic package [1146], the second upper electronic package and the second lower electronic package including: multiple staircased dies, the multiple staircased dies including multiple contact ledges (ledges where [916] and [926] are connected); multiple vertical interconnect bars [502], [504] bonded to the multiple contact ledges; and
a molding layer [1180] (Fig. 11) that encapsulates the multiple staircased dies and the multiple vertical interconnect bars (see Fig. 13).
Regarding claim 19, Zeng in view of Tanaka discloses everything as applied above. Zeng further discloses (Fig. 13) wherein the first set of electronic packages [1046] and the second set of electronic packages [1146] are positioned face-to-face SO that a top surface of the first lower electronic package and a top surface of the second lower electronic package form a package contact ledge, wherein the vertical interconnect array bar [504] spans the package contact ledge (see Fig. 13).
Regarding claim 20, Zeng in view of Tanaka discloses everything as applied above.
Zeng further discloses (Figs. 13, 6) further comprising multiple package routing layers [620] formed over each of the multiple staircased electronic packages [1046], [1146].
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et. al., U. S. Pat. Pub. 2022/0254755, hereafter Zeng, in view of Tanaka, U.S. Pat. Pub. 2023/0411357, hereafter Tanaka, and further in view of Kim et. al., U. S. Pat. Pub. 2021/0288034, hereafter ‘34.
Regarding claim 14, Zeng in view of Tanaka discloses everything as applied above. Tanaka further discloses (Fig. 1)
wherein the first upper electronic package [50] and the first lower electronic package [40] each include:
multiple staircased dies [52], [42], the multiple staircased dies including multiple contact ledges; multiple vertical wire bonds [61], [62] bonded to the multiple contact ledges; and
a molding layer [65] that encapsulates the multiple staircased dies and the multiple vertical wire bonds.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Zeng with the teachings of support and bonding wires of Tanaka to facilitate proper reliable connection between memory dies.
Zeng in view of Tanaka fails to explicitly disclose
wherein the multiple vertical wire bonds extend past a top surface and stand proud above the molding layer.
However, ’34 discloses (Fig. 1C) wherein the multiple vertical wire bonds [11], [13], [15], [17] extend past a top surface [141] and stand proud above the molding layer [40].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Zeng in view of Tanaka with the teachings of vertical wires extending above and standing proud above the molding layer [40] of ’34 to facilitate reliable vertical wire connections between memory dies.
Regarding claim 15, Zeng in view of Tanaka in view of ’34 discloses everything as applied above. Zeng further discloses (Fig. 13, right side) further comprising a second set of electronic packages including a second upper electronic package [1046] and a second lower electronic package[1146], the second upper electronic package and the second lower electronic package including: multiple staircased dies[1046], [1146], the multiple staircased dies including multiple contact ledges (where contacts [916], [926] are connected);
a vertical interconnect array bar [502], [504]; and
a molding layer [1180] (Fig. 11) that encapsulates the multiple staircased electronic packages [1046], [1146] and the vertical interconnect array bar [504], [502].
Zeng fails to explicitly disclose
multiple vertical wire bonds bonded to the multiple contact ledges;
the molding layer encapsulating the one or more support structures.
However, Tanaka further discloses (Fig. 1): multiple vertical wire bonds [61], [62] bonded to the multiple contact ledges; and
the molding layer [65] encapsulating the one or more support structures [32].
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Zeng with the teachings of support and bonding wires of Tanaka to facilitate proper reliable connection between memory dies.
Zeng in view of Tanaka fails to explicitly disclose
wherein the multiple vertical wire bonds extend past a top surface and stand proud above the molding layer.
However, ’34 discloses (Fig. 1C) wherein the multiple vertical wire bonds [11], [13], [15], [17] extend past a top surface [141] and stand proud above the molding layer [40].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Zeng in view of Tanaka with the teachings of vertical wires extending above and standing proud above the molding layer [40] of ’34 to facilitate reliable vertical wire connections between memory dies.
Regarding claim 16, Zeng in view of Tanaka in view of ’34 discloses everything as applied above. Zeng further discloses (Fig. 14)
wherein the first set of electronic packages [1046] and the second set of electronic packages [1146] are positioned face-to-face so that a top surface of the first lower electronic package and a top surface of the second lower electronic package form a package contact ledge, wherein the vertical interconnect array bar [504] ([618] part of [504] shown in Fig. 6) spans the package contact ledge.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights