Prosecution Insights
Last updated: August 15, 2026
Application No. 18/638,600

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Apr 17, 2024
Examiner
REIDA, MOLLY KAY
Art Unit
Tech Center
Assignee
Amkor Technology Singapore Holding Pte. Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
360 granted / 435 resolved
+22.8% vs TC avg
Minimal +2% lift
Without
With
+2.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
22 currently pending
Career history
465
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 435 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species A1 (claims 1-3, 5-7, 11, 12, 14, 15, 17-20) in the reply filed on 07/06/2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/17/2024 has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SEMICONUCTOR PACKAGES. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 5, 11, 14, 15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibuya et al. (US Pub. 2019/0206768). Regarding independent claim 1, Shibuya teaches an electronic device (Fig. 23, Figs. 18-23; para. 0054+), comprising: leads (1806) comprising a conductive material (copper), wherein a lead from the leads includes a base portion and a protrusion extending from a lower side of the base portion (para. 0054-0055); a die paddle (1806) between the leads and comprising the conductive material (para. 0054-0055); a lower mold (2002) on a first lateral side of the protrusion and around lateral sides of the die paddle (para. 0026); a lower surface finish (1826) applied to a lower side of the protrusion (para. 0055); and an electronic component (2200) coupled to the die paddle and in electronic communication with the lead (para. 0057). Re claim 2, Shibuya teaches an upper mold (2204) disposed over the lower mold and around lateral sides of the base portion and the die paddle. Re claim 3, Shibuya teaches wherein the lead is separated from the die paddle by the upper mold and the lower mold (Fig. 23). Re claim 5, Shibuya teaches wherein the lower surface finish is applied to a lower side of the base portion, to a second lateral side of the protrusion opposite the first lateral side of the protrusion, and to the lower side of the protrusion to form a wettable flank (Fig. 23; para. 0055). Re claim 11, Shibuya teaches wherein the lead is enclosed by the lower surface finish, the lower mold, an upper mold disposed around lateral sides of the base portion, and an upper surface finish applied to an upper side of the lead (Fig. 23). Regarding independent claim 14, Shibuya teaches a method of manufacturing an electronic device (Figs. 18-23; para. 0054+), comprising: providing leads (1806) comprising a conductive material (copper), wherein a lead from the leads includes a base portion and a protrusion extending from a lower side of the base portion (para. 0054-0055); providing a die paddle (1806) comprising the conductive material and disposed between the leads (para. 0054-0055); providing a lower mold (2002) on a first lateral side of the protrusion and around lateral sides of the die paddle (para. 0026); applying a lower surface finish (1826) to a lower side of the protrusion (para. 0055); and providing an electronic component (2200) coupled to the die paddle and in electronic communication with the lead (para. 0057). Re claim 15, Shibuya teaches providing an upper mold (2204) over the lower mold and around lateral sides of the base portion and the die paddle (Fig. 23; para. 0057-0058). Re claim 17, Shibuya teaches wherein the lower surface finish is applied to a lower side of the base portion, a second lateral side of the protrusion opposite the first lateral side of the protrusion, and the lower side of the protrusion to form a wettable flank (Fig. 23, para. 0055). Re claim 18, Shibuya teaches wherein the lead is separated from the die paddle by an upper mold (2204) and the lower mold (Fig. 23; para. 0057-0058). Re claim 19, Shibuya teaches wherein the lead is enclosed by the lower surface finish, the lower mold, an upper mold (2204) disposed around lateral sides of the base portion, and an upper surface finish applied to an upper side of the lead (Fig. 23; para. 0057-0058). Regarding independent claim 20, Shibuya teaches an electronic device (Fig. 23, Figs. 18-23; para. 0054+), comprising: a lead (1806) comprising a conductive material (copper) and including a base portion and a protrusion extending from a lower side of the base portion (para. 0054-0055); a die paddle (1806) adjacent the lead and comprising the conductive material (para. 0054-0055); a lower mold (2002) on a first lateral side of the protrusion and around lateral sides of the die paddle, wherein the lower mold is between the lead and the die paddle (Fig. 23; para. 0026); a surface finish (1826) applied to a lower side of the protrusion to form a wettable flank (Fig. 23, para. 0055); and an electronic component (2200) coupled to the die paddle and in electronic communication with the lead (para. 0057). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shibuya et al. (US Pub. 2019/0206768) in view of Jeon et al. (US Pub. 2022/0077031). Re claim 12, Shibuya teaches a variety of materials for the lower surface finish, but is silent with respect to silver-plating, per se. Jeon teaches an electronic device wherein the lower surface finish comprises a silver-plating layer (para. 0038). It would have been obvious to one of ordinary material at the time of filing to use a silver-plating layer as claimed with a reasonable expectation of success for the purpose of preventing lead oxidation (Jeon para. 0038). It is considered prima facie obvious to select a known material based on its suitability for its intended purpose (MPEP 2144.07). Claim(s) 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya et al. (US Pub. 2019/0206768) in view of Park et al. (US Pub. 2011/0049685). Re claims 6 and 7, Shibuya is silent with respect to a shield. Park teaches an electronic device (Figs. 2A-2D) comprising a shield (340) disposed over an electronic component (210) and around lateral sides of the base portion of the lead (130), further comprising a ground lead formed integrally with the die paddle (Fig. 2B) and electrically coupled to the shield (para. 0050, 0058). It would have been obvious to one of ordinary skill in the art at the time of filing to include a shield as taught by Park within the device of Shibuya to arrive at the claimed invention for the purpose of providing EMI protection to the device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 17, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 435 resolved cases by this examiner. Grant probability derived from career allowance rate.

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