DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 7/15/2026 is acknowledged.
Claims 1-6 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/15/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2022/0246573 A1, hereinafter “Chen”).
Regarding independent claim 7, Figure 5 of Chen discloses a semiconductor device, comprising:
a first semiconductor structure 400 (“die”- ¶0017) and a second semiconductor structure 300 (“die”- ¶0017) disposed at different positions on a surface;
an interconnect layer 104 (“interconnect structure”- ¶0015) over the first semiconductor structure 400 and the second semiconductor structure 300, wherein the first semiconductor structure 400 and the second semiconductor structure 300 are coupled through the interconnect layer 104 (¶0021); and
a redistribution layer 602/603/606 (collectively 602 “pads”, 603 “insulating layer” and 606 “conductive bumps”- ¶0031) over the interconnect layer 104, wherein the redistribution layer 602/603/606 is coupled to the interconnect layer 104.
Regarding claim 8, Figure 5 of Chen discloses wherein the redistribution layer 602/603/606 comprises a conductive pad 602 coupled to the interconnect layer 104.
Regarding claim 9, Figure 5 of Chen discloses the semiconductor device further comprising:
an insulating structure 500’ (“encapsulant”- ¶0032) isolating the first semiconductor structure 400 and the second semiconductor structure 300.
Regarding claim 10, Figure 5 of Chen discloses wherein:
the first semiconductor structure 400 comprises a first local interconnect layer 410 (“hybrid bonding structure”- ¶0017) and is coupled to the interconnect layer 104 through the first local interconnect layer 410.
Regarding claim 11, Figure 5 of Chen discloses wherein the second semiconductor structure 300 comprises a second local interconnect layer 310 (“hybrid bonding structure”- ¶0017) and is coupled to the interconnect layer 104 through the second local interconnect layer 310.
Regarding claim 12, Figure 5 of Chen discloses wherein the first semiconductor structure 400 is different from the second semiconductor structure 300.
Regarding claim 13, Figure 5 of Chen discloses wherein:
the first semiconductor structure 400 comprises a logic die (¶0019);
the second semiconductor structure 300 comprises a memory die (¶0019); and
the first semiconductor structure 400 and the second semiconductor structure 300 are formed based on different levels of technology nodes, since the first and second semiconductor structures 400, 300 are different types of die (¶0019) which would require different formation processes.
Additionally, regarding the claim limitation “the first semiconductor structure and the second semiconductor structure are formed based on different levels of technology nodes” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same.
Regarding claim 14, Figure 5 of Chen discloses the semiconductor device further comprising:
a carrier structure 202’ (“block”- ¶0032) bonded to the first semiconductor structure 400 and the second semiconductor structure 300.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al. (US 2022/0336303 A1), which discloses a semiconductor device comprising first and second semiconductor structures disposed adjacent to one another on a surface.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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