DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election of Group I, claims 1-10 in the reply filed on 8/4/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Endoh et al. (US 2013/0119452) in view of Shino (US 2010/0085813).
Re claim 1, Endoh teaches, under BRI, Figs. 1-2 & 15, [0166], a cell structure, comprising:
-a bit line (BL);
-a source line (SL);
-a front gate (upper CG 4);
-a back gate (lower CG 4); and
-a floating body (floating gate 5) having a first surface coupled to the bit line (BL), a second surface coupled to the source line (SL), a third surface coupled to the front gate (upper CG 4), a fourth surface coupled to the back gate (lower CG 4), and wherein the floating body (5) has a selected thickness between the front gate and the back gate (upper & lower CG 4).
Note: coupled # directly/physically coupled/contacted/connected.
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Endoh teaches writing voltage and erase voltage (Fig. 10, [0221]), but does not explicitly teach wherein when the cell is in a data 0 state and selected voltages (*) are supplied to the bit line, the source line, and the front gate and a negative voltage (*) is supplied to the back gate, channel current between the bit line and the source line flows at a first level; and
wherein when the cell is in a data 1 state and the selected voltages (*) are supplied to the bit line, the source line, and the front gate and the negative voltage (*) is supplied to the back gate, the channel current between the bit line and the source line flows at a second level to provide an enlarged current sensing window.
Shino teaches, Figs. 3A & 5, [0074, 0077, 0081, 0085, 0098-0103], when the cell is in data 0 state (data “0”) & in data 1 state (data “1”) [0074, 0077, 0085] & positive voltage applied to gate electrode G & negative voltage applied to the plate [0081]; and voltages applied to memory cells MCs in first & second cycles [0098].
As taught by Shino, one of ordinary skill in the art would utilize & modify the above teaching into Endoh to obtain when the cell is in a data 0 state and selected voltages are supplied to the bit line, the source line, and the front gate and a negative voltage is supplied to the back gate, channel current between the bit line and the source line flows at a first level; and wherein when the cell is in a data 1 state and the selected voltages are supplied to the bit line, the source line, and the front gate and the negative voltage is supplied to the back gate, the channel current between the bit line and the source line flows at a second level to provide an enlarged current sensing window as claimed, because it aids in improving data retention & read/write speed in the formed semiconductor memory.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shino in combination Endoh Ho due to above reason.
(*) The limitations include “selected voltage are supplied” & “negative voltage is supplied” are merely a functional/intended use limitation(s) that do not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claims 2-4, in combination cited above, Shino teaches, under BRI, Figs. 3A & 5, [0074, 0077, 0081, 0085, 0098], wherein when the cell is in the data 0 state (data “0”) and the selected voltages (*) are supplied to the bit line (BL), the source line (SL), and the front gate (G) and the negative voltage (*) is supplied to the back gate (consider a plate formed in substrate 10), a depletion region (e.g., body B can be made fully depleted) is formed in the floating body (B) which restricts the cell current to the first level; wherein the depletion region (formed in B body) is formed in the floating body when the negative voltage (*) supplied to the back gate (the plate) repels electrons in the floating body within a selected depth; wherein the selected depth is equal to or greater than the selected thickness of the floating body (B) (e.g., the body B can be made fully depleted).
Re claim 5, in combination cited above, Shino teaches, under BRI, Figs. 3A & 5, [0074, 0077, 0081, 0085, 0098], wherein when the cell is in the data 1 state (data “1”) and the selected voltages (*) are supplied to the bit line (BL), the source line (SL), and the front gate (G) and the negative voltage (*) is supplied to the back gate (consider a plate in substrate 10), holes stored in the floating body (B) are attracted to the back gate (the pate) form a shield that causes the depletion region (e.g., fully depleted) to disappear and allows the channel current to flow at the second level (Fig. 5).
Re claim 6, in combination cited above, Shino teaches wherein the enlarged current sensing window is determined by the difference between the first level and the second level of the channel current (Fig. 5, different voltage levels [0098-0103]).
Re claims 7 & 8, in combination cited above, Shino teaches wherein the negative voltage (*) is approximately negative one (-1) volts, and wherein the selected voltages (*) include 0 volts supplied to the source line, 0.05 volts supplied to the bit line, and a read voltage in a range of (0.7 to 1 volts) supplied to the front gate (Fig. 5, based on different voltages in cycles, [0098-0103]).
Re claim 9, in combination cited above, Endoh/Shino teaches wherein the selected thickness of the floating body (Endoh, Fig. 1 & Shino, Fig. 3A) is configured to allow the negative voltage (*) supplied to the back gate to modulate channel depth to affect the channel current.
Re claim 10, Endoh teaches wherein the selected thickness of the floating body (5) is equal or less than 20 nanometers (nm) (e.g. based on 5-100 nm of layer 8, Fig. 1, [0169]) (see also Shino, thickness of the SOI layer 30 is 20 nm, Fig. 3A, [0137]).
Further, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose particular thickness, because applicant has not disclosed that, in view of the applied prior art, the thickness is for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the thickness is for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another thickness. Indeed, it has been held that mere thickness limitation(s) is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Furthermore, it would have been obvious to try the particular claimed thickness, because a change in thickness would have been a known option within the technical grasp of a person of ordinary skill in the art and, "a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense." KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007).
Conclusion
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Widjaja (US 2021/0249078, Figs. 1-3) discloses memory cell including a floating body region conjured to be charged to a level indicative of a state of the memory cell.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/12/26
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