DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 10 and 19 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 10 recites “[t]he semiconductor package of claim 1, wherein a plurality of interface pins is configured to contact the plurality of conductive bumps through the respective through holes of the test socket to perform a reliability test of the plurality of circuit patterns and the plurality of redistribution wirings.” Claim 19 has the same recitation. These claims recite the properties of a test socket, but do not appear to recite, directly or indirectly, the properties of claimed semiconductor package. Thus they do not appear to have any bearing on the scope of the claimed semiconductor package.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 10-12, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, US 2024/0079281 A1, in view of Meyer, US 2013/0175686 A1.
Claim 1: Watanabe discloses a semiconductor package comprising
a semiconductor chip (10) having a first surface (12) and a second surface (top, FIG. 9) opposite to the first surface, the semiconductor chip having a plurality of circuit patterns in the second surface ([0053]-[0054]);
a redistribution wiring layer (20) on the second surface of the semiconductor chip,
“The interposer 20 may also perform a pitch conversion of a fine pitch terminals of the quantum chip 10 to/from a pitch for external connection.” [0052].
and a plurality of spacers (47) on the lower surface of the redistribution wiring layer, the plurality of spacers configured to align the plurality of conductive bumps with respective through holes of a test socket (40, [0003]-[0005]) and to space the redistribution wiring layer from the test socket in a first direction perpendicular to the lower surface of the redistribution wiring layer (compare FIG. 1A with FIG. 3B).
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Note that the test socket is not an element of the recited semiconductor package; it is an external element of a testing device. This is limiting on the claim scope only the extent that in requires the ability to align with and space the test socket, which the claimed semiconductor package has.
Watanabe discloses the redistribution of the connection pattern (“pitch conversion”, [0052]) does not illustrate the details of the wiring. However, see Meyer, which discloses
the redistribution wiring layer having a plurality of redistribution wirings (109) and a plurality of bonding pads (110), wherein the plurality of redistribution wirings are electrically connected to the plurality of circuit patterns (Watanabe [0055]), and the plurality of bonding pads (110) are electrically connected to the plurality of redistribution wirings and exposed from a lower surface of the redistribution wiring layer (FIG. 1A); and a plurality of conductive bumps (106) on the plurality of bonding pads, respectively.
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It would have been obvious to have had the redistribution and connection structure recited in claim 1 in Watanabe as a well-known structure in the art for implementing the pitch conversion disclosed by Watanabe.
Claim 2: the plurality of spacers includes first posts respectively in corner regions on the lower surface of the redistribution wiring layer (FIG. 5A).
Claim 3: the plurality of spacers further includes second posts on the lower surface of the redistribution wiring layer and respectively between the plurality of conductive bumps (FIGS. 5B(a), 5B(e), and 5B(i)).
Claim 7: each of the plurality of spacers has one of a cylinder shape, a square pillar shape, a circular cone shape, a quadrangular pyramid shape, a hemisphere shape, a circular truncated cone shape, and a frustum of a quadrangular pyramid shape (FIG. 5A).
Claim 10: a plurality of interface pins (44) is configured to contact the plurality of conductive bumps through the respective through holes of the test socket to perform a reliability test of the plurality of circuit patterns and the plurality of redistribution wirings ([0003]-[0005]).
Note that claim 10 recites elements that are not part of the claimed device (“semiconductor package”): interface pins. These pins are not part of the claimed device. Furthermore, the claimed “reliability test” is an intended use. Thus the scope of claim 10 is limiting only to the extent that the conductive bumps can connect to pins, which Watanabe in view of Meyer discloses that they can.
Claim 11: Watanabe discloses
a semiconductor chip (10) having a plurality of circuit patterns formed therein ([0053]-[0054]);
a redistribution wiring layer (20) provided on the semiconductor chip,
and a plurality of spacers (47), at least a subset of the plurality of spacers respectively in corner regions on the lower surface of the redistribution wiring layer (FIG. 1C), the plurality of spacers configured to space the lower surface of the redistribution wiring layer from an upper surface of a test socket (40+30) that includes a space therein configured to receive the semiconductor chip (FIG. 1A).
Note that the test socket is not an element of the recited semiconductor package; it is an external element of a testing device. It is limiting on the claim scope only the extent that in requires the ability to maintain a space with the test socket, which the claimed semiconductor package has (through the spacer).
Watanabe discloses the redistribution of the connection pattern (“pitch conversion”, [0052]) does not illustrate the details of the wiring. However, see Meyer, which discloses
redistribution wiring layer having a plurality of redistribution wirings (109) and a plurality of bonding pads (110), the plurality of redistribution wirings electrically connected to the plurality of circuit patterns (through 111), the plurality of bonding pads electrically connected to the plurality of redistribution wirings and exposed from a lower surface of the redistribution wiring layer (FIG. 1A); a plurality of conductive bumps (106) on the plurality of bonding pads, respectively.
It would have been obvious to have had the redistribution and connection structure recited in claim 1 in Watanabe as a well-known structure in the art for implementing the pitch conversion disclosed by Watanabe.
Claim 12: at least one of the plurality of spacers is provided in a central region on the lower surface of the redistribution wiring layer (FIG. 5B(e)).
Claim 16: each of the plurality of spacers has one of a cylinder shape, a square pillar shape, a circular cone shape, a quadrangular pyramid shape, a hemisphere shape, a circular truncated cone shape, and a frustum of a quadrangular pyramid shape (FIG. 5A).
Claim 17: Watanabe at [0074]-[0083] states that that the spacer 47 can be made of insulating materials or conductive materials, although specific materials are not listed. However, the claimed materials are common insulating and conductive materials used in semiconductor devices and packaging. See Jae, which discloses rubber material 10 that maintains a constant height with a plate containing pins. It would have been obvious to have used rubber or other claimed materials as known in the art for a similar purpose and/or being obvious as suggested by Watanabe.
Claim 18: Meyer does not disclose the material of the bonding pads 110, but the claimed materials were common and well-known for such bonding pads. See e.g. Zhao, which discloses “Pads 219 may be formed from a metal, metal alloy, multi-metal or multi-alloy stack, such as a multi-alloy stack including a combination of copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), vanadium (V), chromium (Cr), and gold (Au), for example.” [0063]. It would have been obvious to have used such materials as commonly known in the art for pads, of which the examiner takes official notice.
Claim 19: a plurality of interface pins (44) is configured to contact the plurality of conductive bumps through the respective through holes of the test socket to perform a reliability test of the plurality of circuit patterns and the plurality of redistribution wirings ([0003]-[0005]).
Note that claim 19 recites elements that are not part of the claimed device (“semiconductor package”): interface pins. Furthermore, the claimed “reliability test” is an intended use. Thus the scope of claim 10 is limiting only to the extent that the conductive bumps can connect to pins, which Watanabe in view of Meyer discloses that they can.
Claim 20: Watanabe discloses
a semiconductor chip (20) having a first surface (12) and a second surface (top FIG. 9) opposite to the first surface, the semiconductor chip having a plurality of circuit patterns in the second surface ([0053]-[0054]);
a redistribution wiring layer (20) on the second surface of the semiconductor chip,
“The interposer 20 may also perform a pitch conversion of a fine pitch terminals of the quantum chip 10 to/from a pitch for external connection.” [0052].
and a plurality of spacers (47) on the lower surface of the redistribution wiring layer, the plurality of spacers configured to space the redistribution wiring layer from a test socket (40+30) that includes a space therein configured to receive the semiconductor chip, in a first direction (vertical) perpendicular to the lower surface of the redistribution wiring layer (FIG. 1A),
wherein the plurality of spacers includes first posts respectively provided in corner regions on the lower surface of the redistribution wiring layer (FIG. 5A).
Watanabe discloses the redistribution of the connection pattern (“pitch conversion”, [0052]) does not illustrate the details of the wiring. However, see Meyer, which discloses
the redistribution wiring layer having a plurality of redistribution wirings (109) and a plurality of bonding pads (110), wherein the plurality of redistribution wirings are electrically connected to the plurality of circuit patterns (through 111), and the plurality of bonding pads are electrically connected to the plurality of redistribution wirings and exposed from a lower surface of the redistribution wiring layer (FIG. 1A); a plurality of conductive bumps (106) on the plurality of bonding pads, respectively.
It would have been obvious to have had the redistribution and connection structure recited in claim 1 in Watanabe as a well-known structure in the art for implementing the pitch conversion disclosed by Watanabe.
Claims 8 is are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Meyer and Jae, KR 2011-0117389 A. Watanabe at [0074]-[0083] states that that the spacer 47 can be made of insulating materials or conductive materials, although specific materials are not listed. However, the claimed materials are common insulating and conductive materials used in semiconductor devices and packaging. See Jae, [0003], FIGS. 3 and 4 which discloses that a rubber material 10 can be used to maintain constant height with a plate containing pins. It would have been obvious to have used rubber or other claimed materials as known in the art for a similar purpose, as well as other common materials as suggested by Watanabe.
Claims 9 is are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Meyer and Zhao, US 20170011993 A1. Meyer does not disclose the material of the bonding pads 110, but the claimed materials were common and well-known for such bonding pads. See e.g. Zhao, which discloses “Pads 219 may be formed from a metal, metal alloy, multi-metal or multi-alloy stack, such as a multi-alloy stack including a combination of copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), vanadium (V), chromium (Cr), and gold (Au), for example.” [0063]. It would have been obvious to have used such materials as commonly known in the art for pads, of which the examiner takes official notice.
Claims 1-7 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Standing, US 2002/0146861 A1, in view of Hou, US 2021/0057331 A1.
Claim 1: Standing discloses a semiconductor package comprising
a semiconductor chip (10) having a first surface (top) and a second surface (bottom, FIG. 4) opposite to the first surface, the semiconductor chip having a plurality of circuit patterns in the second surface;
and a plurality of spacers (14) on the lower surface (FIG. 4).
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Claim 1 also recites a redistribution wiring layer. Standing does not disclose this, those in the art would understand that contact balls 11 that are illustrated are usually not directly on the circuitry of a chip, as these contacts tend to be very close together, and there is an intervening redistribution layer. See e.g. Hou, which discloses a redistribution wiring layer (112) on the second surface of the semiconductor chip (the side with contacts), the redistribution wiring layer having a plurality of redistribution wirings (112) and a plurality of bonding pads (118), wherein the plurality of redistribution wirings are electrically connected to the plurality of circuit patterns ([0010]-[0011]), and the plurality of bonding pads are electrically connected to the plurality of redistribution wirings and exposed from a lower surface of the redistribution wiring layer (FIG. 1; note that this would be the lower surface in Standing FIG. 4); and a plurality of conductive bumps (120) on the plurality of bonding pads, respectively.
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It would have been obvious to have such a redistribution structure as very common in the art for making external connections to dies.
Claim 1 also recites that the plurality of spacers configured to align the plurality of conductive bumps with respective through holes of a test socket and to space the redistribution wiring layer from the test socket in a first direction perpendicular to the lower surface of the redistribution wiring layer. Note that the test socket is not an element of the recited semiconductor package; it is an external element of a testing device. This is limiting on the claim scope only the extent that in requires the ability to align and space with a test socket, which the claimed semiconductor package has.
Claim 2: the plurality of spacers includes first posts respectively in corner regions on the lower surface of the redistribution wiring layer (the four corner spacers 14 of Standing FIG. 6).
Claim 3: the plurality of spacers further includes second posts on the lower surface of the redistribution wiring layer and respectively between the plurality of conductive bumps (Standing FIG. 6).
Claim 4: each of the plurality of spacers has a third height extending from the lower surface of the redistribution wiring layer in the first direction, and each of the plurality of conductive bumps has a second height extending from the lower surface of the redistribution wiring layer in the first direction, the second height being greater than the third height (standing FIG. 4).
Claim 5: the third height of the spacers is not set forth by Standing. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV).
Furthermore, Standing discloses that “discrete spaced columns of an underfill plastic are deposited, in the wafer stage and prior to singulation, between solder balls and to a height equal to the final standoff height of the reflowed die.” [0006]. Thus the height of the spacers is a result effective variable, and would be within ordinary skill in the art to determine.
Claim 6: Standing in view of Hou does not disclose the height of the bonding pads. However, it would have been obvious to have made the height of the bonding pads (first height) less than the height of the height of the spacers (third height), as this would prevent the bonding pad from hitting the device to which it is to be bonded.
Claim 7: each of the plurality of spacers has one of a cylinder shape, a square pillar shape, a circular cone shape, a quadrangular pyramid shape, a hemisphere shape, a circular truncated cone shape, and a frustum of a quadrangular pyramid shape (cylinder, Standing FIGS. 3 and 4).
Claim 11: Standing disclose
a semiconductor chip (10) having a plurality of circuit patterns formed therein;
and a plurality of spacers (14), at least a subset of the plurality of spacers respectively in corner regions (corner spacers 14 in FIG. 3) on the lower surface of the redistribution wiring layer.
Claim 11 also recites a redistribution wiring layer. Standing does not disclose this, those in the art would understand that contact balls 11 that are illustrated are usually not directly on the circuitry of a chip, as these contacts tend to be very close together, and there is an intervening redistribution layer. See e.g. Hou, which discloses a redistribution wiring layer provided on the semiconductor chip, the redistribution wiring layer (112) having a plurality of redistribution wirings and a plurality of bonding pads (118), the plurality of redistribution wirings electrically connected to the plurality of circuit patterns ([0010]-[0011]), the plurality of bonding pads electrically connected to the plurality of redistribution wirings and exposed from a lower surface of the redistribution wiring layer (FIG. 1; note that this would be the lower surface in Standing FIG. 4); and a plurality of conductive bumps (120) on the plurality of bonding pads, respectively. It would have been obvious to have such a redistribution structure as very common in the art for making external connections to dies.
Claim 11 also recites that the plurality of spacers are configured to space the lower surface of the redistribution wiring layer from an upper surface of a test socket that includes a space therein configured to receive the semiconductor chip. This is an intended use. The spacers are capable of spacing the lower surface of the redistribution wiring layer for various things, including a test socket.
Claim 12: at least one of the plurality of spacers is provided in a central region on the lower surface of the redistribution wiring layer (Standing FIG. 3).
Claim 13: each of the plurality of spacers has a third height extending from the lower surface of the redistribution wiring layer in a first direction perpendicular to the lower surface of the redistribution wiring layer, and each of the plurality of conductive bumps has a second height extending from the lower surface of the redistribution wiring layer in the first direction, the second height being greater than the third height (Standing FIG. 4).
Claim 14: the third height of the spacers is not set forth by Standing. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV).
Furthermore, Standing discloses that “discrete spaced columns of an underfill plastic are deposited, in the wafer stage and prior to singulation, between solder balls and to a height equal to the final standoff height of the reflowed die.” [0006]. Thus the height of the spacers is a result effective variable, and would be within ordinary skill in the art to determine.
Claim 15: Standing in view of Hou does not disclose the height of the bonding pads. However, it would have been obvious to have made the height of the bonding pads (first height) less than the height of the height of the spacers (third height), as this would prevent the bonding pad from hitting the device to which it is to be bonded.
Claim 16: each of the plurality of spacers has one of a cylinder shape, a square pillar shape, a circular cone shape, a quadrangular pyramid shape, a hemisphere shape, a circular truncated cone shape, and a frustum of a quadrangular pyramid shape (cylinder, Standing FIGS. 3 and 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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