DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 depends on claim 17, in apparent error. Claim 16 recites limitations in reference to features of claim 15. There is insufficient antecedent basis for the limitations of claim 16.
Claims 17 and 18 depend on claim 16, and likewise recite limitations in reference to features of claim 15, and therefore, similarly lack antecedent basis.
For purposes of examination, claim 16 has been interpreted as dependent on claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6-8, 12, 15, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim (US 7,385,253).
In reference to claim 1, Kim (US 7,385,253, hereafter “Kim,” discloses a semiconductor device, with reference to Figure 4, comprising: a substrate 401;
an N-well area 404 formed in the substrate;
a P-channel metal oxide semiconductor (PMOS) transistor including a first P-type active region 412 and a second P-type active region 414 formed in the N-well area; and
a N-channel metal oxide semiconductor (NMOS) transistor including a first N-type active region 410 and a second N-type active region 409 formed in the substrate,
wherein the first N-type active region 410 overlaps the N-well area, when viewed from above a plane parallel to a top surface of the substrate,
wherein the first N-type active region includes at least one first N+ implant area 411, col. 6 lines 21-53,
wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F.
In reference to claim 3, Kim discloses wherein at least a portion of the at least one first N+ implant area 411 overlaps the N-well area 404 when viewed from above the plane.
In reference to claim 6, Kim discloses a doping concentration of each of the first and second N-type active regions is higher than a doping concentration of the N-well area, col. 6 lines 40-53, (implied by the N+ notation on 409 and 411 and the region 410 in well 404 receiving the well implant and the additional “low-concentration impurity ion implant”).
In reference to claim 7, Kim discloses a doping concentration of each of at least one first N+ implant area is higher than the doping concentration of each of the first and second N-type active regions, col. 6 lines 40-53, (implied by the N+ notation on 409 and 411 and the region 411 in region 410 and well 404 receiving those additional implants).
In reference to claim 8, Kim discloses the second N-type active region 409 includes at least one second N+ implant area.
In reference to claim 12, Kim discloses the first P-type active region 412 is electrically connected to the first N-type active region 410, Vdd in Figure 4 and col. 7 lines 10-13.
In reference to claim 15, Kim discloses a semiconductor device, with reference to Figure 4, comprising:
a first transistor including a first gate 406, a first active region 410 and a second active region 409; and
a second transistor including a second gate 407, a third active region 412 and a fourth active region 414 formed in the substrate, col. 6 lines 21-53,
wherein a body bias of the second transistor is directly provided by the first active region, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 7,385,253) in view of Ker et al. (US 7,542,253).
In reference to claim 2, Kim does not disclose the at least one first N+ implant area is 2 or more.
Ker et al. (US 7,542,253), hereafter “Ker,” discloses an analogous semiconductor device including teaching the at least one first N+ implant area, 11, 13 in Figure 7, is 2 or more, col. 5 lines 32-37. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first N+ implant area to be 2 or more. One would have been motivated to do so in order to provide an electrostatic discharge path between terminals with an added trigger to increase the turn on speed, col. 7 lines 48-53.
In reference to claim 9, Kim does not disclose a number of the at least one first N+ implant area is different from a number of the at least one second N+ implant area.
Ker teaches a number of the at least one first N+ implant area (3), N+ regions 11, 13 to the left of gate Mn in Figure 7, is different from a number (1) of the at least one second N+ implant area, to the right of gate Mn in Figure 7. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a number of the at least one first N+ implant area to be different from a number of the at least one second N+ implant area. One would have been motivated to do so in order to provide an electrostatic discharge path between terminals with an added trigger to increase the turn on speed, col. 7 lines 48-53.
Claims 4, 5, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 7,385,253) in view of Aurola (US 2018/0026639).
In reference to claim 4, Kim does not disclose the at least one first N+ implant area has a polygonal shape.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching a first N+ implant area, 4516 in Figure 46, has a polygonal shape, Figure 46 and paragraph 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first N+ implant area to have a polygonal shape. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
In reference to claim 5, Kim does not disclose the first N-type active region has a polygonal shape.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching a first N-type active region, 731 in Figure 46, has a polygonal shape, Figure 46 and paragraph 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first N-type active region to have a polygonal shape. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
In reference to claim 11, Kim does not disclose when viewed from above the plane, a shape of the first N-type active region is different from a shape of the second N-type active region.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching when viewed from above the plane, a shape of the first N-type active region, 4516 in Figure 46, is different from a shape of the second N-type active region 711, Figure 46 and paragraphs 329 and 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a shape of the first N-type active region to be different from a shape of the second N-type active region when viewed from above the plane. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
Claims 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 7,385,253).
In reference to claim 16, Kim discloses electrical connection between the first active region 410 and the third active region 412, (Vdd) col. 7 lines 10-13.
Kim is silent regarding a first metal line.
The examiner takes OFFICIAL NOTICE that it is well known in the art for such electrical connections between source and drain regions to be formed by a metal line. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a first metal line to be electrically connected between the first active region and the third active region. One would have been motivated to do so in order to provide interconnection between devices for operation of an electronic component using standard back-end-of-line metallization layers.
In reference to claim 18, Kim discloses a power supply voltage, Vss: positive in Figures 5A and 5E, is provided to the second active region 409, col. 7 lines 27-33.
In reference to claim 19, Kim discloses a semiconductor device, with reference to Figure 4, comprising:
a P-channel metal oxide semiconductor (PMOS) transistor including a first PMOS terminal 412 and a second PMOS terminal, 414, and a first gate terminal, 407; and
a N-channel metal oxide semiconductor (NMOS) transistor including a first NMOS terminal 409 and a second NMOS terminal 410, and a second gate terminal, 406,
wherein the first PMOS terminal and the second NMOS terminal are electrically connected to each other, col. 6 lines 21-53,
wherein a body bias of the PMOS transistor is directly provided by a first N-type active region of the NMOS transistor, the first N-type active region electrically connected to the second NMOS terminal, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F.
Kim is silent regarding wherein the first PMOS terminal and the second NMOS terminal being electrically connected to each other through a first metal line.
The examiner takes OFFICIAL NOTICE that it is well known in the art for such electrical connections between source and drain regions to be formed by a metal line. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first PMOS terminal and the second NMOS terminal to be electrically connected to each other through a first metal line. One would have been motivated to do so in order to provide interconnection between devices for operation of an electronic component using standard back-end-of-line metallization layers.
In reference to claim 20, Kim discloses the PMOS transistor is formed in an N-well area, 404, formed in a substrate, at least part of the first N-type active region overlaps the N-well area when viewed from above a plane parallel to a top surface of the substrate, implied by the cross-section of Figure 4.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,990,475. Although the claims at issue are not identical, they are not patentably distinct from each other. The “a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area; and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate” of the patent implies the respective first and second active regions of claim 1. The more specific claim of the patent anticipates the broader claim 1.
Claims 1, 3, 6-10, 12, 14-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,990,475 in view of Kim (US 7,385,253).
In reference to claim 1, claim 1 of the patent includes all of the limitations of claim 1 except wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region.
Kim discloses an analogous semiconductor device including teaching wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a body bias of the first PMOS transistor to be provided directly through the first N-type active region. One would have been motivated to do so in order to provide a high voltage electro-static discharge device, col. 6 lines 16-20.
In reference to claim 3, claim 12 of the patent includes all of the limitations of claim 3.
In reference to claim 6, Kim discloses a doping concentration of each of the first and second N-type active regions is higher than a doping concentration of the N-well area, col. 6 lines 40-53, (implied by the N+ notation on 409 and 411 and the region 410 in well 404 receiving the well implant and the additional “low-concentration impurity ion implant”).
In reference to claim 7, Kim discloses a doping concentration of each of at least one first N+ implant area is higher than the doping concentration of each of the first and second N-type active regions, col. 6 lines 40-53, (implied by the N+ notation on 409 and 411 and the region 411 in region 410 and well 404 receiving those additional implants).
In reference to claim 8, claim 11 of the patent includes all of the limitations of claim 8.
In reference to claim 9, claim 13 of the patent includes all of the limitations of claim 9.
In reference to claim 10, claim 14 of the patent includes all of the limitations of claim 10.
In reference to claim 12, Kim discloses the first P-type active region 412 is electrically connected to the first N-type active region 410, Vdd in Figure 4 and col. 7 lines 10-13.
In reference to claim 14, claim 15 of the patent includes all of the limitations of claim 14.
In reference to claim 15, claim 18 of the patent includes all of the limitations of claim 15 except wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region.
Kim discloses an analogous semiconductor device including teaching wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a body bias of the first PMOS transistor to be provided directly through the first N-type active region. One would have been motivated to do so in order to provide a high voltage electro-static discharge device, col. 6 lines 16-20.
In reference to claim 16, Kim discloses electrical connection between the first active region 410 and the third active region 412, (Vdd) col. 7 lines 10-13.
Kim is silent regarding a first metal line.
The examiner takes OFFICIAL NOTICE that it is well known in the art for such electrical connections between source and drain regions to be formed by a metal line. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a first metal line to be electrically connected between the first active region and the third active region. One would have been motivated to do so in order to provide interconnection between devices for operation of an electronic component using standard back-end-of-line metallization layers.
In reference to claim 18, Kim discloses a power supply voltage, Vss: positive in Figures 5A and 5E, is provided to the second active region 409, col. 7 lines 27-33.
In reference to claim 19, claim 18 of the patent includes all of the limitations of claim 19 except wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region.
Kim discloses an analogous semiconductor device including teaching wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region, (Vdd) col. 7 lines 10-13 and Figures 5C, 5D, and 5F. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a body bias of the first PMOS transistor to be provided directly through the first N-type active region. One would have been motivated to do so in order to provide a high voltage electro-static discharge device, col. 6 lines 16-20.
In reference to claim 20, claim 18 of the patent includes all of the limitations of claim 20.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,990,475 in view of Kim (US 7,385,253) and Ker et al. (US 7,542,253).
In reference to claim 2, claim 1 of the patent in view of Kim includes all of the limitations of claim 2 except the at least one first N+ implant area is 2 or more.
Ker discloses an analogous semiconductor device including teaching the at least one first N+ implant area, 11, 13 in Figure 7, is 2 or more, col. 5 lines 32-37. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first N+ implant area to be 2 or more. One would have been motivated to do so in order to provide an electrostatic discharge path between terminals with an added trigger to increase the turn on speed, col. 7 lines 48-53.
Claims 4, 5, and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,990,475 in view of Kim (US 7,385,253) and Aurola (US 2018/0026639).
In reference to claim 4, claim 1 of the patent in view of Kim does not disclose the at least one first N+ implant area has a polygonal shape.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching a first N+ implant area, 4516 in Figure 46, has a polygonal shape, Figure 46 and paragraph 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first N+ implant area to have a polygonal shape. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
In reference to claim 5, claim 1 of the patent in view of Kim does not disclose the first N-type active region has a polygonal shape.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching a first N-type active region, 731 in Figure 46, has a polygonal shape, Figure 46 and paragraph 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first N-type active region to have a polygonal shape. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
In reference to claim 11, claim 1 of the patent in view of Kim does not disclose when viewed from above the plane, a shape of the first N-type active region is different from a shape of the second N-type active region.
Aurola (US 2018/0026639) discloses an analogous semiconductor device, including teaching when viewed from above the plane, a shape of the first N-type active region, 4516 in Figure 46, is different from a shape of the second N-type active region 711, Figure 46 and paragraphs 329 and 396. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a shape of the first N-type active region to be different from a shape of the second N-type active region when viewed from above the plane. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, shaping analogous doped regions in a similar way.
Allowable Subject Matter
Claims 13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 would be allowable because the prior art of record fails to teach or fairly suggest the structure comprising the NMOS transistor includes a first gate electrically connected to the second P-type active region; in combination with the other recited limitations in the respective claims and their base claims.
Claim 17 would be allowable because the prior art of record fails to teach or fairly suggest the structure comprising a second metal line electrically connected between the first gate and the fourth active region; in combination with the other recited limitations in the respective claims and their base claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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