DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed February 13, 2026 has been entered. Claims 1-3, 5-6, 9-19, and 21-32 remain pending in this application. Claims 4, 7-8, and 20 cancelled at applicant’s request. Claims 1, 12, 17, 23, and 24 have been amended. Claims 27-32 have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed November 17, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6, 9-12, 14-17, 22-27, 29, and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0287599 A1 to Yusuke Higashi, et al. (hereafter Higashi) in view of US 2021/0057416 A1 to Jiyoung Kim, et al. (hereafter Kim) and further in view of US 5,270,967 to Reza Moazzami, et al. (hereafter Moazzami) and US 9,899,084 B2 to Zhen Li, et al. (hereafter Li).
Regarding Independent Claim 1, Higashi discloses a semiconductor memory device, comprising:
a memory cell array (A memory cell array: Higashi, ¶[0036]) including:
a first semiconductor layer (A semiconductor layer: Higashi, ¶[0054])
extending in a first direction (The semiconductor layer extending in the Y direction: Higashi, ¶[0054]);
a plurality of gate electrode layers stacked in the first direction (Gate electrode layers stacked in the first direction: Higashi, Figure 2);
a first wiring electrically connected to one end of the first semiconductor layer (First wiring SL connected to one end of the first semiconductor layer: Higashi, Figure 2);
a second wiring electrically connected to the other end of the first semiconductor layer (Second wiring BL connected to the second end of the first semiconductor layer: Higashi, Figure 2); and
a plurality of first memory cells (A plurality of memory cells: Higashi, Figure 2), each of the plurality of first memory cells including
a part of the first semiconductor layer (Each memory cell including the semiconductor layer 203: Higashi, ¶[0055] and Higashi, Figure 4),
one of the plurality of gate electrode layers (Each memory cell including the conductive layer 202: Higashi, ¶[0055] and Higashi, Figure 4), and
a gate insulating layer including (A gate insulating layer: Higashi, ¶[0055] and Higashi, Figure 4)
provided between the part of the first semiconductor layer and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4); and
a control circuit configured to control the plurality of first memory cells (Control circuit controlling the memory array: Higashi, ¶[0032]), wherein
the control circuit is configured to perform a write operation on one first memory cell (Control circuit performing a write operation on a memory cell: Higashi, ¶[0042]) selected from the plurality of first memory cells, and
in the write operation configured to
apply a first voltage pulse (Applying a first voltage pulse: Higashi, ¶[0116])
having a first voltage with a first polarity and a first pulse width (Describing the application of voltage having a voltage, polarity, and pulse width: Higashi, ¶[0094]; Note: The first pulse described here is in reference to a different pulse than a write operation, the description of the terms would be the same, however.)
between the one of the plurality of gate electrode layers of the one first memory cell (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]) and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to perform an erase operation on the plurality of first memory cells (Disclosing an erase operation: Higashi, ¶[0121]), and
in the erase operation configured to
apply a second voltage pulse (Applying a second voltage pulse: Higashi, ¶[0121])
having a second voltage with a second polarity opposite to the first polarity and a second pulse width (The second voltage having a polarity opposite to the first polarity: Higashi, Figure 5; Pulse width is inherent to an erase pulse)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
determine whether or not the number of times of execution of the erase operation on the plurality of first memory cells (Tracking the number of write/erase cycles performed: Higashi, ¶[0097])
has reached a first predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]),
the control circuit is configured to
perform first processing on the plurality of first memory cells (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
when it is determined that the number of times of execution has reached the first predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]), and
in the first processing configured to
apply a third voltage pulse (Applying a third voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092]) having
a third voltage with the first polarity (The third voltage being positive, matching the polarity of the first voltage: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the first voltage (The absolute value of the third voltage being the same or larger than the first voltage pulse: Higashi, ¶[0093]) and
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
perform second processing on the plurality of first memory cells (Performing a processing operation on a set of memory cells: Higashi, ¶[0092]) after the first processing (The second processing taking place after the first processing: Higashi, ¶[0092]), and
in the second processing configured to
apply a fourth voltage pulse (Applying a fourth voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092]) having
a fourth voltage with the second polarity (The fourth voltage polarity being negative matching the second polarity: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the second voltage (The absolute value of the fourth voltage being the same or larger than the second voltage pulse: Higashi, ¶[0093]) and
a fourth pulse width (A voltage pulse having a pulse width is inherent)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the gate insulating layer further includes
a second insulating region between the first insulating region and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4) and
a charge storage region between the first insulating region and the second insulating region (A charge storage region located between the insulating layers between the gate electrode and semiconductor base: Higashi, ¶[0055] and Higashi, Figure 4),
the charge storage region is configured to trap and store charges,
a threshold voltage of a transistor of each of the plurality of first memory cells changes according to an amount of charges stored in the charge storage region (Threshold voltage changing based on the charge state of the charge storage region: Higashi, ¶[0048]), and
each of the plurality of first memory cells is configured to store data based on the threshold voltage (Threshold voltage of cell corresponding to different data states: Higashi, Figure 11).
While Higashi discloses an insulating layer in the memory cell (Higashi, Figure 4), it does not specify the composition of the insulating material. Kim, however, discloses a memory device wherein:
a first insulating region containing silicon (Si), oxygen (O), and nitrogen (N) (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]) and
the first insulating region includes silicon oxynitride (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]),
the charge storage region includes silicon nitride (Disclosing using silicon nitride as the central insulating, charge storage, layer: Kim, ¶[0083]), and
the second insulating region includes silicon oxide or aluminum oxide (Disclosing silicon oxide as an insulating material: Kim, ¶[0053]),
Kim teaches this material serves as a high-k dielectric (Kim, ¶[0049]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the high-k dielectric material of Kim with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell construction and the combination of known inventions with predictable results is obvious and not patentable.
Neither Higashi nor Kim disclose specific pulse width wherein the second pulse, the erase pulse, is longer than the first write/program pulse. Li, however, discloses an operation wherein the second pulse is longer than the first pulse (Disclosing an erase pulse being longer than a write pulse: Li, col.12:4-11). Li teaches limiting the duration of the first pulse relative to the second pulse minimizes program errors (Li, col.5:2-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the write pulse error limitations of Li with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
None of the prior cited prior art disclose a pulse length for a refresh or re-wake-up operation. Moazzami, however, discloses a memory device wherein
a third pulse width larger than the first pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4)
the third pulse width is larger than the second pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4).
Moazzami discloses the extended refresh pulse width enhances the refresh operation beyond merely increasing the voltage (Moazzami, col.13:11-16). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse duration of Moazzami with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 6 and the substantially similar limitations of Claim 22, Higashi discloses the semiconductor memory device according to claim 1,
wherein the absolute value of the third voltage is larger than the absolute value of the first voltage (The absolute value of the third voltage being larger than the first voltage pulse: Higashi, ¶[0093]).
Regarding Claim 9, Higashi discloses the semiconductor memory device according to claim 1,
wherein the first polarity is a polarity causing the one of the plurality of gate electrode layers to have a positive voltage with respect to at least one of the first wiring or the second wiring (The first voltage being a positive voltage: Higashi, Figure 5), and
the second polarity is a polarity causing the one of the plurality of gate electrode layers to have a negative voltage with respect to at least one of the first wiring or the second wiring (The second voltage being a negative voltage: Higashi, Figure 5).
Regarding Claim 10, Higashi discloses the semiconductor memory device according to claim 1, wherein the control circuit is configured to
perform the second processing without performing the write operation between the first processing and the second processing (Applying the positive and negative pulses to the memory cell without performing a write operation between the positive pulse and the negative pulse: Higashi, ¶[0092]).
Regarding Claim 11, Higashi discloses the semiconductor memory device according to claim 1, wherein the control circuit is configured to
perform the first processing without performing the write operation between the erase operation and the first processing (Performing the re-wake-up operation after the erase operation without performing a write operation between: Higashi, ¶[0096]).
Regarding Claim 12, Higashi discloses the semiconductor memory device according to claim 1, wherein the memory cell array further includes:
a second semiconductor layer (A second semiconductor layer: Higashi, ¶[0054] and Higashi, Figure 2) extending in the first direction (The second semiconductor layer extending in the Y direction: Higashi, ¶[0054]),
one end of the second semiconductor layer connected to the first wiring (First wiring SL connected to one end of the second semiconductor layer: Higashi, Figure 2);
a third wiring connected to the other end of the second semiconductor layer (Third wiring BL connected to the second end of the second semiconductor layer: Higashi, Figure 2); and
a plurality of second memory cells (A plurality of memory cells: Higashi, Figure 2), each of the plurality of second memory cells including
a part of the second semiconductor layer (Each memory cell including the semiconductor layer 203: Higashi, ¶[0055] and Higashi, Figure 4),
one of the plurality of gate electrode layers (Each memory cell including the conductive layer 202: Higashi, ¶[0055] and Higashi, Figure 4), and
a gate insulating layer including a third insulating region containing silicon (Si), oxygen (O), and nitrogen (N) (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]) and
provided between the part of the second semiconductor layer and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4),
the control circuit is further configured to control the plurality of second memory cells (Control circuit controlling the memory array: Higashi, ¶[0032]), and
the control circuit is configured to perform a write operation on one second memory cell (Control circuit performing a write operation on a memory cell: Higashi, ¶[0042]) selected from the plurality of second memory cells, and
in the write operation configured to
apply the first voltage pulse (Applying a first voltage pulse: Higashi, ¶[0116])
between the one of the plurality of gate electrode layers of the one second memory cell and at least one of the first wiring or the third wiring (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]),
in the erase operation configured to
apply the second voltage pulse (Applying a second voltage pulse: Higashi, ¶[0121])
between each of the gate electrode layers of the plurality of second memory cells and at least one of the first wiring or the third wiring (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]),
in the first processing configured to
apply the third voltage pulse (Applying a third voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092])
between each of the gate electrode layers of the plurality of second memory cells and at least one of the first wiring or the third wiring (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]), and
in the second processing configured to
apply the fourth voltage pulse (Applying a fourth voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092])
between each of the gate electrode layers of the plurality of second memory cells and at least one of the first wiring or the third wiring (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]).
Regarding Claim 14, Higashi discloses the semiconductor memory device according to claim 13. Further, Higashi discloses the negative phase of the re-wake-up operation being complementary to the positive phase, suggesting the phases are of equal duration (Higashi, ¶[0093]). Therefore, given the third and fourth pulses are of the same duration, and the fifth pulse is of longer duration than the third pulse, and the fifth and sixth pulses are of the same duration, then the sixth pulse must necessarily be longer than the fourth pulse.
Regarding Claim 15 and the substantially similar limitations of Claim 25, Higashi discloses the semiconductor memory device according to claim 1, wherein,
in the first processing, an application of the third voltage pulse between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring is performed simultaneously for the plurality of first memory cells (Performing the re-wake-up operation on individual memory cells, a page of memory cells, or the entire block of memory cells: Higashi, ¶[0095]).
Regarding Claim 16 and the substantially similar limitations of Claim 26, Higashi discloses the semiconductor memory device according to claim 1, wherein,
in the first processing, an application of the third voltage pulse between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring is performed for each group obtained by dividing the plurality of first memory cells into a plurality of groups (Performing the re-wake-up operation on individual memory cells, a page of memory cells, or the entire block of memory cells: Higashi, ¶[0095]).
Regarding Independent Claim 17, Higashi discloses a semiconductor memory device, comprising:
a memory cell (A memory cell array: Higashi, ¶[0036]) including
a semiconductor layer (A semiconductor layer: Higashi, ¶[0054]),
a gate electrode layer (Gate electrode layer: Higashi, Figure 4), and
a gate insulating layer (A gate insulating layer: Higashi, ¶[0055] and Higashi, Figure 4)
provided between the semiconductor layer and the gate electrode layer (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4);
a first wiring (First wiring SL connected to one end of the first semiconductor layer: Higashi, Figure 2) and a second wiring electrically connected to the semiconductor layer (Second wiring BL connected to the second end of the first semiconductor layer: Higashi, Figure 2); and
a control circuit configured to control the memory cell (Control circuit controlling the memory array: Higashi, ¶[0032]),
wherein the control circuit is configured to
perform a write operation on the memory cell (Control circuit performing a write operation on a memory cell: Higashi, ¶[0042]), and
in the write operation configured to
apply a first voltage pulse (Applying a first voltage pulse: Higashi, ¶[0116])
having a first voltage with a first polarity and a first pulse width (Describing the application of voltage having a voltage, polarity, and pulse width: Higashi, ¶[0094])
between the gate electrode layer (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]) and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
perform an erase operation on the memory cell (Disclosing an erase operation: Higashi, ¶[0121]), and
in the erase operation configured to
apply a second voltage pulse (Applying a second voltage pulse: Higashi, ¶[0121])
having a second voltage with a second polarity opposite to the first polarity and a second pulse width (The second voltage having a polarity opposite to the first polarity: Higashi, Figure 5; Pulse width is inherent to an erase pulse)
between the gate electrode layer and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
determine whether or not the number of times of execution of the erase operation on the memory cell (Tracking the number of write/erase cycles performed: Higashi, ¶[0097]) has reached a predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]),
the control circuit is configured to
perform first processing on the memory cell (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
when it is determined that the number of times of execution has reached the predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]), and
in the first processing configured to
apply a third voltage pulse (Applying a third voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092])
having a third voltage with the first polarity (The third voltage being positive, matching the polarity of the first voltage: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the first voltage (The absolute value of the third voltage being the same or larger than the first voltage pulse: Higashi, ¶[0093]) and
between the gate electrode layer and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
perform second processing on the memory cell (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
after the first processing (The second processing taking place after the first processing: Higashi, ¶[0092]), and
in the second processing configured
to apply a fourth voltage pulse (Applying a fourth voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092])
having a fourth voltage with the second polarity (The fourth voltage polarity being negative matching the second polarity: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the second voltage (The absolute value of the fourth voltage being the same or larger than the second voltage pulse: Higashi, ¶[0093]) and
a fourth pulse width (A voltage pulse having a pulse width is inherent)
between the gate electrode layer and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the gate insulating layer further includes
a second insulating region between the first insulating region and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4) and
a charge storage region between the first insulating region and the second insulating region (A charge storage region located between the insulating layers between the gate electrode and semiconductor base: Higashi, ¶[0055] and Higashi, Figure 4),
the charge storage region is configured to trap and store charges,
a threshold voltage of a transistor of each of the plurality of first memory cells changes according to an amount of charges stored in the charge storage region (Threshold voltage changing based on the charge state of the charge storage region: Higashi, ¶[0048]), and
each of the plurality of first memory cells is configured to store data based on the threshold voltage (Threshold voltage of cell corresponding to different data states: Higashi, Figure 11).
While Higashi discloses an insulating layer in the memory cell (Higashi, Figure 4), it does not specify the composition of the insulating material. Kim, however, discloses a memory device wherein:
a first insulating region containing silicon (Si), oxygen (O), and nitrogen (N) (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]) and
the first insulating region includes silicon oxynitride (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]),
the charge storage region includes silicon nitride (Disclosing using silicon nitride as the central insulating, charge storage, layer: Kim, ¶[0083]), and
the second insulating region includes silicon oxide or aluminum oxide (Disclosing silicon oxide as an insulating material: Kim, ¶[0053]),
Kim teaches this material serves as a high-k dielectric (Kim, ¶[0049]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the high-k dielectric material of Kim with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell construction and the combination of known inventions with predictable results is obvious and not patentable.
Neither Higashi nor Kim disclose specific pulse width wherein the second pulse, the erase pulse, is longer than the first write/program pulse. Li, however, discloses an operation wherein the second pulse is longer than the first pulse (Disclosing an erase pulse being longer than a write pulse: Li, col.12:4-11). Li teaches limiting the duration of the first pulse relative to the second pulse minimizes program errors (Li, col.5:2-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the write pulse error limitations of Li with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
None of the prior cited prior art disclose a pulse length for a refresh or re-wake-up operation. Moazzami, however, discloses a memory device wherein
a third pulse width larger than the first pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4)
the third pulse width is larger than the second pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4).
Moazzami discloses the extended refresh pulse width enhances the refresh operation beyond merely increasing the voltage (Moazzami, col.13:11-16). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse duration of Moazzami with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 23, Higashi discloses a semiconductor memory device, comprising:
a first semiconductor layer (A semiconductor layer: Higashi, ¶[0054]) extending in a first direction (The semiconductor layer extending in the Y direction: Higashi, ¶[0054]);
a first gate electrode layer and a second gate electrode layer arranged in the first direction (A first and second electrode layer arranged in the first direction: Higashi, Figure 2);
a gate insulating layer including (A gate insulating layer: Higashi, ¶[0055] and Higashi, Figure 4)
the gate insulating layer provided between the first semiconductor layer and the first gate electrode layer (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4), and
the gate insulating layer provided between the first semiconductor layer and the second gate electrode layer (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4);
a first memory cell including (A plurality of memory cells: Higashi, Figure 2)
a part of the first semiconductor layer (Each memory cell including the semiconductor layer 203: Higashi, ¶[0055] and Higashi, Figure 4),
the first gate electrode layer (Each memory cell including the conductive layer 202: Higashi, ¶[0055] and Higashi, Figure 4), and
the gate insulating layer (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4);
a second memory cell including (A plurality of memory cells: Higashi, Figure 2)
a part of the first semiconductor layer (Each memory cell including the semiconductor layer 203: Higashi, ¶[0055] and Higashi, Figure 4),
the second gate electrode layer (Each memory cell including the conductive layer 202: Higashi, ¶[0055] and Higashi, Figure 4), and
the gate insulating layer (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4);
a first wiring electrically connected to one end of the first semiconductor layer (First wiring SL connected to one end of the first semiconductor layer: Higashi, Figure 2);
a second wiring electrically connected to the other end of the first semiconductor layer (Second wiring BL connected to the second end of the first semiconductor layer: Higashi, Figure 2); and
a control circuit configured to control the first memory cell and the second memory cell (Control circuit controlling the memory array: Higashi, ¶[0032]),
wherein the control circuit is configured to
perform a write operation on the first memory cell (Control circuit performing a write operation on a memory cell: Higashi, ¶[0042]), and
in the write operation configured to
apply a first voltage pulse (Applying a first voltage pulse: Higashi, ¶[0116])
having a first voltage with a first polarity and a first pulse width (Describing the application of voltage having a voltage, polarity, and pulse width: Higashi, ¶[0094])
between the first gate electrode layer (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]) and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
perform an erase operation on the first memory cell and the second memory cell (Disclosing an erase operation: Higashi, ¶[0121]), and
in the erase operation configured to
apply a second voltage pulse (Applying a second voltage pulse: Higashi, ¶[0121])
having a second voltage with a second polarity opposite to the first polarity and a second pulse width (The second voltage having a polarity opposite to the first polarity: Higashi, Figure 5; Pulse width is inherent to an erase pulse)
between each of the first gate electrode layer and the second gate electrode layer and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the control circuit is configured to
determine whether or not the number of times of execution of the erase operation on the first memory cell and the second memory cell (Tracking the number of write/erase cycles performed: Higashi, ¶[0097])
has reached a first predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]),
the control circuit is configured to
perform first processing on the first memory cell and the second memory cell (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
when it is determined that the number of times of execution has reached the first predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]), and
in the first processing configured to
apply a third voltage pulse (Applying a third voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092]) having
a third voltage with the first polarity (The third voltage being positive, matching the polarity of the first voltage: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the first voltage (The absolute value of the third voltage being the same or larger than the first voltage pulse: Higashi, ¶[0093]) and
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2), and
the control circuit is configured to
perform second processing
on the first memory cell and the second memory cell (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
after the first processing (The second processing taking place after the first processing: Higashi, ¶[0092]), and
in the second processing configured to
apply a fourth voltage pulse (Applying a fourth voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092]) having
a fourth voltage with the second polarity (The fourth voltage polarity being negative matching the second polarity: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the second voltage (The absolute value of the fourth voltage being the same or larger than the second voltage pulse: Higashi, ¶[0093]) and
a fourth pulse width (A voltage pulse having a pulse width is inherent)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the gate insulating layer further includes
a second insulating region between the first insulating region and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4) and
a charge storage region between the first insulating region and the second insulating region (A charge storage region located between the insulating layers between the gate electrode and semiconductor base: Higashi, ¶[0055] and Higashi, Figure 4),
the charge storage region is configured to trap and store charges,
a threshold voltage of a transistor of each of the plurality of first memory cells changes according to an amount of charges stored in the charge storage region (Threshold voltage changing based on the charge state of the charge storage region: Higashi, ¶[0048]), and
each of the plurality of first memory cells is configured to store data based on the threshold voltage (Threshold voltage of cell corresponding to different data states: Higashi, Figure 11).
While Higashi discloses an insulating layer in the memory cell (Higashi, Figure 4), it does not specify the composition of the insulating material. Kim, however, discloses a memory device wherein:
a first insulating region containing silicon (Si), oxygen (O), and nitrogen (N) (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]) and
the first insulating region includes silicon oxynitride (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]),
the charge storage region includes silicon nitride (Disclosing using silicon nitride as the central insulating, charge storage, layer: Kim, ¶[0083]), and
the second insulating region includes silicon oxide or aluminum oxide (Disclosing silicon oxide as an insulating material: Kim, ¶[0053]),
Kim teaches this material serves as a high-k dielectric (Kim, ¶[0049]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the high-k dielectric material of Kim with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell construction and the combination of known inventions with predictable results is obvious and not patentable.
Neither Higashi nor Kim disclose specific pulse width wherein the second pulse, the erase pulse, is longer than the first write/program pulse. Li, however, discloses an operation wherein the second pulse is longer than the first pulse (Disclosing an erase pulse being longer than a write pulse: Li, col.12:4-11). Li teaches limiting the duration of the first pulse relative to the second pulse minimizes program errors (Li, col.5:2-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the write pulse error limitations of Li with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
None of the prior cited prior art disclose a pulse length for a refresh or re-wake-up operation. Moazzami, however, discloses a memory device wherein
a third pulse width larger than the first pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4)
the third pulse width is larger than the second pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4).
Moazzami discloses the extended refresh pulse width enhances the refresh operation beyond merely increasing the voltage (Moazzami, col.13:11-16). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse duration of Moazzami with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 24, Higashi discloses a method for controlling a semiconductor memory device including
a memory cell array (A memory cell array: Higashi, ¶[0036]) including:
a first semiconductor layer (A semiconductor layer: Higashi, ¶[0054])
extending in a first direction (The semiconductor layer extending in the Y direction: Higashi, ¶[0054]);
a plurality of gate electrode layers stacked in the first direction (Gate electrode layers stacked in the first direction: Higashi, Figure 2);
a first wiring electrically connected to one end of the first semiconductor layer (First wiring SL connected to one end of the first semiconductor layer: Higashi, Figure 2);
a second wiring electrically connected to the other end of the first semiconductor layer (Second wiring BL connected to the second end of the first semiconductor layer: Higashi, Figure 2); and
a plurality of first memory cells (A plurality of memory cells: Higashi, Figure 2), each of the plurality of first memory cells including
a part of the first semiconductor layer (Each memory cell including the semiconductor layer 203: Higashi, ¶[0055] and Higashi, Figure 4),
one of the plurality of gate electrode layers (Each memory cell including the conductive layer 202: Higashi, ¶[0055] and Higashi, Figure 4), and
a gate insulating layer (A gate insulating layer: Higashi, ¶[0055] and Higashi, Figure 4)
provided between the part of the first semiconductor layer and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4),
the method comprising:
performing a write operation on one first memory cell selected from the plurality of first memory cells (Performing a write operation on a memory cell: Higashi, ¶[0042]),
in the write operation
applying a first voltage pulse (Applying a first voltage pulse: Higashi, ¶[0116])
having a first voltage with a first polarity and a first pulse width (Describing the application of voltage having a voltage, polarity, and pulse width: Higashi, ¶[0094])
between the one of the plurality of gate electrode layers of the one first memory cell (Applying the write voltage to a word line, shown connected to the control gate of the memory cells: Higashi, ¶[0116]) and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2);
performing an erase operation on the plurality of first memory cells (Disclosing an erase operation: Higashi, ¶[0121]),
in the erase operation
applying a second voltage pulse (Applying a second voltage pulse: Higashi, ¶[0121])
having a second voltage with a second polarity opposite to the first polarity and a second pulse width (The second voltage having a polarity opposite to the first polarity: Higashi, Figure 5; Pulse width is inherent to an erase pulse)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2);
determining whether or not the number of times of execution of the erase operation (Tracking the number of write/erase cycles performed: Higashi, ¶[0097])
has reached a predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]);
performing first processing on the plurality of first memory cells (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
when it is determined that the number of times of execution has reached the predetermined number of times (Comparing the number of write/erase cycles to a predetermined number: Higashi, ¶[0097]),
in the first processing
applying a third voltage pulse (Applying a third voltage during a ‘Re-Wake-Up’ process: Higashi, ¶[0092])
having a third voltage with the first polarity (The third voltage being positive, matching the polarity of the first voltage: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the first voltage (The absolute value of the third voltage being the same or larger than the first voltage pulse: Higashi, ¶[0093]) and
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2); and
performing second processing on the plurality of first memory cells (Performing a processing operation on a set of memory cells: Higashi, ¶[0092])
after the first processing (The second processing taking place after the first processing: Higashi, ¶[0092]),
in the second processing
applying a fourth voltage pulse having a fourth voltage with the second polarity (The fourth voltage polarity being negative matching the second polarity: Higashi, ¶[0092]) and
an absolute value equal to or more than an absolute value of the second voltage (The absolute value of the fourth voltage being the same or larger than the second voltage pulse: Higashi, ¶[0093]) and
a fourth pulse width (A voltage pulse having a pulse width is inherent)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2),
the gate insulating layer further includes
a second insulating region between the first insulating region and the one of the plurality of gate electrode layers (Each memory cell including insulating layers 206: Higashi, ¶[0055] and Higashi, Figure 4) and
a charge storage region between the first insulating region and the second insulating region (A charge storage region located between the insulating layers between the gate electrode and semiconductor base: Higashi, ¶[0055] and Higashi, Figure 4),
the charge storage region is configured to trap and store charges,
a threshold voltage of a transistor of each of the plurality of first memory cells changes according to an amount of charges stored in the charge storage region (Threshold voltage changing based on the charge state of the charge storage region: Higashi, ¶[0048]), and
each of the plurality of first memory cells is configured to store data based on the threshold voltage (Threshold voltage of cell corresponding to different data states: Higashi, Figure 11).
While Higashi discloses an insulating layer in the memory cell (Higashi, Figure 4), it does not specify the composition of the insulating material. Kim, however, discloses a memory device wherein:
a first insulating region containing silicon (Si), oxygen (O), and nitrogen (N) (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]) and
the first insulating region includes silicon oxynitride (Disclosing using silicon oxynitride as an insulating material: Kim, ¶[0049]),
the charge storage region includes silicon nitride (Disclosing using silicon nitride as the central insulating, charge storage, layer: Kim, ¶[0083]), and
the second insulating region includes silicon oxide or aluminum oxide (Disclosing silicon oxide as an insulating material: Kim, ¶[0053]),
Kim teaches this material serves as a high-k dielectric (Kim, ¶[0049]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the high-k dielectric material of Kim with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell construction and the combination of known inventions with predictable results is obvious and not patentable.
Neither Higashi nor Kim disclose specific pulse width wherein the second pulse, the erase pulse, is longer than the first write/program pulse. Li, however, discloses an operation wherein the second pulse is longer than the first pulse (Disclosing an erase pulse being longer than a write pulse: Li, col.12:4-11). Li teaches limiting the duration of the first pulse relative to the second pulse minimizes program errors (Li, col.5:2-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the write pulse error limitations of Li with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
None of the prior cited prior art disclose a pulse length for a refresh or re-wake-up operation. Moazzami, however, discloses a memory device wherein
a third pulse width larger than the first pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4)
the third pulse width is larger than the second pulse width (Disclosing a refresh operation wherein the refresh pulse is extended compared to a write or rewrite operation: Moazzami, col.13:16-19 and Moazzami, Figure 4).
Moazzami discloses the extended refresh pulse width enhances the refresh operation beyond merely increasing the voltage (Moazzami, col.13:11-16). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse duration of Moazzami with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Regarding New Claim 27 and the substantially similar limitations of Claims 29 and 31, Kim discloses the semiconductor memory device according to Claim 1, wherein
the first insulating region is in direct contact with the part of the first semiconductor layer (The first line in direct contact with the first insulating region: Kim, Figure 3),
the charge storage region is in direct contact with the first insulating region (The first insulating region in direct contact with the charge storage region: Kim, Figure 3),
the second insulating region is in direct contact with the charge storage region (The charge storage region in direct contact with the second insulating region: Kim, Figure 3), and
the one of the plurality of gate electrode layers is in direct contact with the second insulating region (The second insulating region in direct contact with the gate electrode layer: Kim, Figure 3).
Claim(s) 2 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0287599 A1 to Yusuke Higashi, et al. (hereafter Higashi), US 2021/0057416 A1 to Jiyoung Kim, et al. (hereafter Kim), US 5,270,967 to Reza Moazzami, et al. (hereafter Moazzami), and US 9,899,084 B2 to Zhen Li, et al. (hereafter Li) in view of US 2021/0125656 A1 to Stefan Müller (hereafter Müller).
Regarding Claim 2 and the substantially similar limitations of Claim 18, Higashi discloses the semiconductor memory device according to claim 1, but fails to disclose the further limitations of Claims 2 and 18. Müller, however discloses a memory device as in Claim 1 wherein,
wherein the third pulse width is equal to or more than 10 msec and equal to or less than 1 sec (Disclosing a pre-conditioning pulse lasting anywhere from 10ns to 1500ms: Müller, ¶[0159]).
Müller teaches the preconditioning signal within this duration may remove any effects that may have occurred during a storage period, restoring a predefined condition to the memory cell (Müller, ¶[0045]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse of Müller with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 3 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0287599 A1 to Yusuke Higashi, et al. (hereafter Higashi), US 2021/0057416 A1 to Jiyoung Kim, et al. (hereafter Kim), US 5,270,967 to Reza Moazzami, et al. (hereafter Moazzami), and US 9,899,084 B2 to Zhen Li, et al. (hereafter Li) in view of US 2021/0125656 A1 to Stefan Müller (hereafter Müller) and further in view of A. Sheikholeslami and P. G. Gulak, "A survey of circuit innovations in ferroelectric random-access memories," in Proceedings of the IEEE, vol. 88, no. 5, pp. 667-689, May 2000 (hereafter Sheikholeslami).
Regarding Claim 3 and the substantially similar limitations of Claim 19, Higashi discloses the semiconductor memory device according to claim 1 but fails to explicitly disclose the further limitations of claims 3 and 19. Sheikholeslami, however, discloses a standard write time for a ferroelectric memory cell to be ~100ns (Disclosing a standard write access time for a ferroelectric memory cell being ~100ns: Sheikholeslami, Table 1). Further, Müller, discloses a preconditioning pulse wherein the preconditioning pulse width is 10 times or greater (Disclosing a pre-conditioning pulse lasting anywhere from 10ns to 1500ms, far exceeding the 1000ns benchmark: Müller, ¶[0159]) than the first pulse width.
Müller teaches the preconditioning signal within this duration may remove any effects that may have occurred during a storage period, restoring a predefined condition to the memory cell (Müller, ¶[0045]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the extended refresh pulse of Müller with the re-wake-up process of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of refreshing ferroelectric memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 5 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0287599 A1 to Yusuke Higashi, et al. (hereafter Higashi), US 2021/0057416 A1 to Jiyoung Kim, et al. (hereafter Kim), US 5,270,967 to Reza Moazzami, et al. (hereafter Moazzami), and US 9,899,084 B2 to Zhen Li, et al. (hereafter Li) in view of A. Sheikholeslami and P. G. Gulak, "A survey of circuit innovations in ferroelectric random-access memories," in Proceedings of the IEEE, vol. 88, no. 5, pp. 667-689, May 2000 (hereafter Sheikholeslami).
Regarding Claim 5 and the substantially similar limitations of Claim 21, Higashi discloses the semiconductor memory device according to claim 1, but does not expressly disclose the fourth pulse width being larger than the second pulse width. Sheikholeslami, however, teaches the first write pulse and second erase pulse may be effected by pulses of the same duration (Sheikholeslami, page 670 §B ¶5). Higashi discloses the negative phase of the re-wake-up operation being complementary to the positive phase, suggesting the phases are of equal duration (Higashi, ¶[0093]). Therefore, given the first and second pulses are of the same duration, and the third pulse is of longer duration than the first pulse, and the third and fourth pulses are of the same duration, then the fourth pulse must necessarily be longer than the second pulse.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0287599 A1 to Yusuke Higashi, et al. (hereafter Higashi), US 2021/0057416 A1 to Jiyoung Kim, et al. (hereafter Kim), US 5,270,967 to Reza Moazzami, et al. (hereafter Moazzami), and US 9,899,084 B2 to Zhen Li, et al. (hereafter Li) in view of US 10,964,385 B1 to Lingming Yang, et al. (hereafter Yang).
Regarding Claim 13, Higashi discloses the semiconductor memory device according to claim 1,
wherein the control circuit is configured to
determine whether or not the number of times of execution of the erase operation on the plurality of first memory cells (Tracking the number of write/erase cycles performed: Higashi, ¶[0097]) (Tracking the number of write/erase cycles performed: Higashi, ¶[0097])
after the second processing has reached a second predetermined number of times (Executing the re-wake-up operation every predetermined number of write/erase cycles: Higashi, ¶[0097]),
the control circuit is configured to
perform third processing on the plurality of first memory cells
when it is determined that the number of times of execution has reached the second predetermined number of times (Executing the re-wake-up operation every predetermined number of write/erase cycles: Higashi, ¶[0097]), and
in the third processing configured to
apply a fifth voltage pulse having a fifth voltage with the first polarity (The refresh voltage being positive, matching the polarity of the first voltage: Higashi, ¶[0092]) and
an absolute value equal to or more than the absolute value of the first voltage (The absolute value of the refresh voltage being the same or larger than the first voltage pulse: Higashi, ¶[0093]) and
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2), and
the control circuit is configured to
perform fourth processing on the plurality of first memory cells (Performing an additional processing operation on a set of memory cells: Higashi, ¶[0092])
after the third processing (The negative processing pulse taking place after the positive processing pulse: Higashi, ¶[0092]), and
in the fourth processing configured to
apply a sixth voltage pulse having a sixth voltage with the second polarity (The negative voltage polarity being negative: Higashi, ¶[0092]) and
an absolute value equal to or more than the absolute value of the second voltage (The absolute value of the negative voltage being the same or larger than the erase voltage pulse: Higashi, ¶[0093]) and
a sixth pulse width (A voltage pulse having a pulse width is inherent)
between each of the gate electrode layers of the plurality of first memory cells and at least one of the first wiring or the second wiring (Memory cells and their gates located between first and second wiring: Higashi, Figure 2).
Higashi does not explicitly teach a second round refresh operation wherein the refresh pulse applied the second time is longer than the pulse applied during the first refresh operation. Yang, however, discloses a second refresh operation as in Claim 12 wherein second refresh pulse width is larger than the first refresh operation pulse width (Disclosing a second refresh operation wherein the duration of the refresh pulse in the second refresh operation is longer than the pulse duration in the first refresh pulse: Yang, col.17:61-67). Yang discloses the long duration refresh pulse may serve to change the threshold voltage of the memory cell so that it falls within the range appropriate for the memory device (Yang, col.2:13-17). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the long duration second refresh operation of Yang with the first refresh operation of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory cell refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
Allowable Subject Matter
Claim(s) 28, 30, and 32 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest, either individually or in combination, the claimed invention wherein the third pulse width is larger than the fourth pulse width.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0392535 A1 to Karthik Sarpatwari, et al.: Disclosing a memory array wherein positive and negative voltages are applied to reduce voltage threshold drift.
US 2007/0183208 A1 to Masayuki Tanaka, et al.: Disclosing detrapping pulses applied to a ferroelectric memory array.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824