CTNF 18/638,939 CTNF 89716 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on April 18, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 14 was rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 14, which depends on claim 1, recites “… wherein: a dummy solder bump is further disposed in at least a partial region between the first bump pad and a top of the first semiconductor chip, or between the second bump pad and a bottom of the second semiconductor chip” ( emphasis added by the Examiner ). The Examiner could not find any description in the specification that clarifies the term “dummy solder bump”, its roles or functions, the material it is composed of etc. Because of lack of any understanding what “dummy solder bump” is in the context of the current application, it could not be examined against any prior arts. Appropriate correction/clarification is requested. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, and 15-16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. ( Pub. No. : US 2021/0265297 A1 ) . Regarding Claim 1, Kim et al. discloses a semiconductor package, comprising: a first semiconductor chip ( Par. 0027-0030; Figs. 1-10 – first semiconductor chip 110 ); a second semiconductor chip disposed on the first semiconductor chip ( Par. 0027-0030; Figs. 1-10 – second semiconductor chip 120 ); and PNG media_image1.png 470 574 media_image1.png Greyscale a bump structure disposed between the first semiconductor chip and the second semiconductor chip, the bump structure electrically connecting the first semiconductor chip and the second semiconductor chip to each other ( Par. 0027-0054; Figs. 1-10 – bump structure comprising first bump 116 and second bump 126 ), wherein the bump structure includes a first bump pad and a second bump pad disposed on a same plane as each other, and a solder bump disposed between the first bump pad and the second bump pad, the solder bump abutting on a side of the first bump pad and a side of the second bump pad ( Par. 0027-0054; Figs. 1-10 – first bump pad 116B (first shell portion); second bump pad 126B (second shell portion); solder bump comprising 116A (first core portion) and 126A (second core portion) ). Regarding Claim 2, Kim et al., as applied to claim 1, discloses the semiconductor package, wherein: the first bump pad and the second bump pad are spaced apart from each other by the solder bump ( Figs. 1-10 ). Regarding Claim 3, Kim et al., as applied to claim 2, discloses the semiconductor package, wherein: the first bump pad and the second bump pad are symmetrically disposed on a plane relative to the solder bump ( Figs 7-8 ); and the first bump pad and the second bump pad have a same area as each other ( Figs 7-8 ). Regarding Claim 4, Kim et al., as applied to claim 1, discloses the semiconductor package, wherein: at least a portion of the first bump pad and the second bump pad are disposed in direct contact with each other ( Figs 1-10 ). Regarding Claim 5, Kim et al., as applied to claim 4, discloses the semiconductor package, wherein: the first bump pad and the second bump pad have different areas on the plane ( Figs 5-6 ). Regarding Claim 15, Kim et al., as applied to claim 1, discloses the semiconductor package, wherein: a first insulator is disposed on a top of the first semiconductor chip, the first insulator abuts on the first bump pad, the second bump pad, and the solder bump ( Par. 0028; Figs. 3-4 – not stated explicitly but implied ). Regarding Claim 16, Kim et al. discloses a semiconductor package, comprising: a base chip including a base TSV ( Par. 0103-0115; Fig 10 – first chip 510 may be considered as the base chip; base TSV 514 ); a plurality of semiconductor chips disposed on the base chip, the plurality of semiconductor chips are electrically connected to each other via a plurality of TSVs ( Par. 0103-0115; Fig 10 – semiconductor chips 520, 530, 540 etc.; TSVs 524; 534 etc. ); an adhesive layer disposed between the base chip and the plurality of semiconductor chips, and between each of the plurality of semiconductor chips ( Par. 0103-0115; Fig 10 – filling material 550 could be considered as the adhesive layer ); and a sealant surrounding sides of the plurality of semiconductor chips and the adhesive layer ( Par. 0103-0115; Fig 10 – sealant 560 (molding layer ), wherein the plurality of semiconductor chips includes a bump structure disposed therebetween, the bump structure electrically connecting the plurality of semiconductor chips to each other via the plurality of TSVs ( Par. 0103-0115; Fig 10 – bump structure comprising BS3’, BS4’ etc. ), the bump structure includes a first bump pad and a second bump pad disposed on a same plane as each other, and a solder bump disposed between the first bump pad and the second bump pad, the solder bump abutting on a side of the first bump pad and a side of the second bump pad ( Par. 0103-0115; Fig 10 – first bump pad SP1’ on the left of CP1’ and second bump pad SP1’ on the right of CP1’; solder bump CP1’ ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 6-13 and 17 are rejected under 35 U.S.C. 103 as obvious over Kim et al. ( Pub. No. : US 2021/0265297 A1 ) , as applied to claim 4 and claim 16, respectively. Regarding Claim 6, Kim et al., as applied to claim 4, is silent regarding the semiconductor package, wherein: the ratio of a horizontal direction length of the solder bump to a horizontal direction length of the bump structure is in a range of about 5/40 to about 15/50. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the ratio of a horizontal direction length of the solder bump to a horizontal direction length of the bump structure is in a range of about 5/40 to about 15/50. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the ratio of a horizontal direction length of the solder bump to a horizontal direction length of the bump structure is in a range of about 5/40 to about 15/50. since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 7, Kim et al., as applied to claim 6, is silent regarding the semiconductor package, wherein: the horizontal direction length of the bump structure is in a range of about 40 µm to about 50 µm. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the horizontal direction length of the bump structure is in a range of about 40 µm to about 50 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the horizontal direction length of the bump structure is in a range of about 40 µm to about 50 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 8, Kim et al., as applied to claim 1, is silent regarding the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a horizontal direction length of the bump structure is in a range of about 1/50 to about 5/40. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a horizontal direction length of the bump structure is in a range of about 1/50 to about 5/40. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a horizontal direction length of the bump structure is in a range of about 1/50 to about 5/40, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 9, Kim et al., as applied to claim 8, discloses the semiconductor package, wherein: the gap between the top surface of the first semiconductor chip and the bottom surface of the second semiconductor chip is greater than 0 µm ( Fig. 10 ) Kim et al. is silent regarding the semiconductor package, wherein: the gap between the top surface of the first semiconductor chip and the bottom surface of the second semiconductor chip is less than or equal to about 5 µm. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the gap between the top surface of the first semiconductor chip and the bottom surface of the second semiconductor chip is less than or equal to about 5 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the gap between the top surface of the first semiconductor chip and the bottom surface of the second semiconductor chip is less than or equal to about 5 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 10, Kim et al., as applied to claim 1, discloses the semiconductor package, wherein: the bump structure is disposed in plurality between the first semiconductor chip and the second semiconductor chip ( Fig. 10 ) Kim et al. is silent regarding the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a gap between centers of adjacent bump structures of the plurality of bump structures is in a range of about 40/60 to about 60/40. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Furthermore, gap between centers of adjacent bump structures of the plurality of bump structures could not be arbitrarily small as this could increase possibility of shorting and increased crosstalk. Kim et al. discloses the claimed invention except for t the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a gap between centers of adjacent bump structures of the plurality of bump structures is in a range of about 40/60 to about 60/40. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the ratio of a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to a gap between centers of adjacent bump structures of the plurality of bump structures is in a range of about 40/60 to about 60/40, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 11, Kim et al., as applied to claim 10, is silent regarding the semiconductor package, wherein: the gap between the centers of the adjacent bump structures is in a range of about 50 µm to about 60 µm. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Furthermore, gap between centers of adjacent bump structures of the plurality of bump structures could not be arbitrarily small as this could increase possibility of shorting and increased crosstalk. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the gap between the centers of the adjacent bump structures is in a range of about 50 µm to about 60 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the gap between the centers of the adjacent bump structures is in a range of about 50 µm to about 60 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 12, Kim et al., as applied to claim 1, discloses the semiconductor package, wherein: the bump structure is disposed in plurality between the first semiconductor chip and the second semiconductor chip ( Fig. 10 ) Kim et al. is silent regarding the semiconductor package, wherein: a gap between opposing sidewalls of adjacent bump structures of the plurality of bump structures relative to a gap between centers of the adjacent bump structures of the plurality of bump structures in in a range of about 15/50 to about 25/40. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Furthermore, gap between centers of adjacent bump structures of the plurality of bump structures could not be arbitrarily small as this could increase possibility of shorting and increased crosstalk. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: a gap between opposing sidewalls of adjacent bump structures of the plurality of bump structures relative to a gap between centers of the adjacent bump structures of the plurality of bump structures in in a range of about 15/50 to about 25/40. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: a gap between opposing sidewalls of adjacent bump structures of the plurality of bump structures relative to a gap between centers of the adjacent bump structures of the plurality of bump structures in in a range of about 15/50 to about 25/40, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 13, Kim et al., as applied to claim 12, is silent regarding the semiconductor package, wherein: the gap between the opposing sidewalls of the adjacent bump structures is in a range of about 15 µm to about 25 µm. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Furthermore, gap between centers of adjacent bump structures of the plurality of bump structures could not be arbitrarily small as this could increase possibility of shorting and increased crosstalk. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: the gap between the opposing sidewalls of the adjacent bump structures is in a range of about 15 µm to about 25 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: the gap between the opposing sidewalls of the adjacent bump structures is in a range of about 15 µm to about 25 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding Claim 17, Kim et al., as applied to claim 16, discloses the semiconductor package, wherein: a gap between the plurality of semiconductor chips is greater than 0 µm ( Fig. 10 ) Kim et al. is silent regarding the semiconductor package, wherein: a gap between the plurality of semiconductor chips is less than or equal to about 5 µm. However, just looking at the drawings of Kim et al. , although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. This prior art teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Kim et al. discloses the claimed invention except for the semiconductor package, wherein: a gap between the plurality of semiconductor chips is less than or equal to about 5 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: a gap between the plurality of semiconductor chips is less than or equal to about 5 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Claims 18-19 are rejected under 35 U.S.C. 103 as obvious over Kim et al. (Patent No.: US 2019/0221520 A1) in view of Kim et al. ( Pub. No. : US 2021/0265297 A1 ), hereinafter referred to as Kim (‘297). Regarding Claim 18, Kim et al. discloses a semiconductor device, comprising: a package substrate ( Par. 0081-0091; Fig. 8 – package substrate 500 ); an interposer mounted on the package substrate ( Par. 0081-0091; Fig. 8 –interposer 200 ); PNG media_image2.png 410 532 media_image2.png Greyscale at least one semiconductor package mounted on the interposer ( Par. 0081-0091; Fig. 8 – semiconductor package substrate 100 ); and a processor chip arranged side by side with the semiconductor package and mounted on the interposer ( Par. 0081-0091; Fig. 8 – processor chip 300 ), wherein each of the at least one semiconductor package comprises: a base chip connected to the interposer ( Par. 0081-0091; Fig. 8 in conjunction with Fig. 1 – base chip 110 ); a plurality of semiconductor chips stacked on the base chip ( Par. 0081-0091; Fig. 8 in conjunction with Fig. 1 – semiconductor chips 120-1, 120-2 etc. ); and at least one first bump structure disposed between the plurality of semiconductor chips, the at least one first bump structure electrically connecting the plurality of semiconductor chips to each other ( Par. 0081-0091; Fig. 8 in conjunction with Fig. 1 – bump structure comprising bums 128 ), each of the at least one first bump structure includes a first bump pad and a second bump pad disposed on a same plane as each other, and a solder bump disposed between the first bump pad and the second bump pad ( Par. 0054; 0081-0091; Figs. 4A-8 in conjunction with Fig. 1 – first bump pad 125; second bump pad 128p; solder bump 128s ). Kim et al. does not disclose the solder bump abutting on sides of the first bump pad and the second bump pad However, Kim (‘297) teaches the solder bump abutting on sides of the first bump pad and the second bump pad ( Par. 0103-0115; Fig 10 – first bump pad SP1’ on the left of CP1’ and second bump pad SP1’ on the right of CP1’; solder bump CP1’ ). PNG media_image1.png 470 574 media_image1.png Greyscale Kim et al. teaches a way of minimizing solder sweeping phenomena by intentionally shifting the pads in peripheral regions outward relative to the TSV/bump centerline ( please see Figs. 4A-4B ). However, this structure is still susceptible to bump collapse and/or bridging issues between neighboring bumps. Kim (‘297) , on the other hand, teaches a structure wherein a low-melting core is surrounded by a high melting shell and confines the molten core to a restricted space. This structure prevents bump collapsing as the shells act as rigid dams and also prevents bridging. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Kim (‘297) to adapt a semiconductor device, comprising: wherein the solder bump of Kim et al. abutting on sides of the first bump pad and the second bump pad in order to prevent bridge failure and allow finer pitch interconnects. Regarding Claim 19, modified Kim et al., as applied to claim 18, discloses the semiconductor device, further comprising: a second bump structure electrically connecting the semiconductor package and the interposer, wherein the second bump structure includes a third bump pad and a fourth bump pad disposed on a same plane as each other, and a second solder bump disposed between the third bump pad and the fourth bump pad, the second solder bump abutting on a side of the third bump pad and a side of the fourth bump pad ( obvious in light of rejection of claim 18; also see Kim et al. - Par. 0054; 0081-0091; Figs. 8-9 in conjunction with Fig. 1 together with Kim (‘297 ) - Par. 0103-0115; Fig 10 ). Claim 20 is rejected under 35 U.S.C. 103 as obvious over Kim et al. (Patent No.: US 2019/0221520 A1) and Kim et al. ( Pub. No. : US 2021/0265297 A1 ), hereinafter referred to as Kim (‘297), as applied to claim 18. Regarding Claim 20, modified Kim et al., as applied to claim 18, discloses the semiconductor package, wherein: a gap between the plurality of semiconductor chips in the semiconductor package is greater than 0 µm ( Kim (‘297 ) - Fig. 10 ) Modified Kim et al. is silent regarding the semiconductor package, wherein: a gap between the plurality of semiconductor chips in the semiconductor package is less than or equal to about 5 µm. However, just looking at the drawings of Modified Kim et al. ( Kim (‘297 ) - Fig. 10 ), although the drawings might not have been drawn to scale, it gives some ideas about the workable ranges. Kim (‘297 ) teaches that by laterally surrounding the low-temperature solder core with a high-temperature shell, a bridge failure could be avoided ( Par. 0056 ). It further teaches that collapse of the bump structure could also be avoided through use of rigid shell surrounding the softer solder core ( Par. 0057 ). Now, it should be clear at once that the horizontal direction length of the shell of Kim (which corresponds to the bump pads of the instant application) compared to the horizontal direction length of the solder bump should be such that both the bridge failure and bump collapse could be avoided without consuming too much space and at the same time achieve good electrical connection. The horizontal direction length of the solder bump should be no more than what is required to secure stable electrical connection between the first bump pad and the second bump pad. The horizontal direction length of the first bump pad and the second bump pad should be thick enough to make sure bump collapse does not happen. At the same time, it should be as thin as possible to make sure that it does not become an obstacle to achieving fine pitch interconnections. In other words, horizontal direction length of the entire bump structure could be reduced as long as the overall device performance is not negatively impacted. Furthermore, a gap between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip could also be significantly reduced due to the presence of rigid bump pads whose height can be set according to the desired gap. Now, the minimum gap that could be achieved would also depend on other factors such as the density of the bump structures, the materials used for the bump pads, the thickness of the chips, the details of the electrical structures running in each chip etc. Modified Kim et al. discloses the claimed invention except for the semiconductor package, wherein: a gap between the plurality of semiconductor chips in the semiconductor package is less than or equal to about 5 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein: a gap between the plurality of semiconductor chips in the semiconductor package is less than or equal to about 5 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (Pub. No.: US 2017/0200688 A1) – This prior art teaches a semiconductor package, comprising: a first semiconductor chip ( 10 ); a second semiconductor chip ( 20 ) disposed on the first semiconductor chip; and a bump structure ( 30+18 ) disposed between the first semiconductor chip and the second semiconductor chip, the bump structure electrically connecting the first semiconductor chip and the second semiconductor chip to each other, wherein the bump structure includes a first bump pad ( 18 ) and a second bump pad ( 32 ) disposed on a same plane as each other, and a solder bump ( 34 ) disposed between the first bump pad and the second bump pad, the solder bump abutting on a side of the first bump pad and a side of the second bump pad ( Fig. 1 ). Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 06/12/2026 /SYED I GHEYAS/Primary Examiner, Art Unit 2893 Application/Control Number: 18/638,939 Page 2 Art Unit: 2893 Application/Control Number: 18/638,939 Page 3 Art Unit: 2893 Application/Control Number: 18/638,939 Page 4 Art Unit: 2893 Application/Control Number: 18/638,939 Page 5 Art Unit: 2893 Application/Control Number: 18/638,939 Page 6 Art Unit: 2893 Application/Control Number: 18/638,939 Page 7 Art Unit: 2893 Application/Control Number: 18/638,939 Page 8 Art Unit: 2893 Application/Control Number: 18/638,939 Page 9 Art Unit: 2893 Application/Control Number: 18/638,939 Page 10 Art Unit: 2893 Application/Control Number: 18/638,939 Page 11 Art Unit: 2893 Application/Control Number: 18/638,939 Page 12 Art Unit: 2893 Application/Control Number: 18/638,939 Page 13 Art Unit: 2893 Application/Control Number: 18/638,939 Page 14 Art Unit: 2893 Application/Control Number: 18/638,939 Page 15 Art Unit: 2893 Application/Control Number: 18/638,939 Page 16 Art Unit: 2893 Application/Control Number: 18/638,939 Page 17 Art Unit: 2893 Application/Control Number: 18/638,939 Page 18 Art Unit: 2893 Application/Control Number: 18/638,939 Page 19 Art Unit: 2893 Application/Control Number: 18/638,939 Page 20 Art Unit: 2893 Application/Control Number: 18/638,939 Page 21 Art Unit: 2893 Application/Control Number: 18/638,939 Page 22 Art Unit: 2893 Application/Control Number: 18/638,939 Page 23 Art Unit: 2893 Application/Control Number: 18/638,939 Page 24 Art Unit: 2893 Application/Control Number: 18/638,939 Page 25 Art Unit: 2893 Application/Control Number: 18/638,939 Page 26 Art Unit: 2893 Application/Control Number: 18/638,939 Page 27 Art Unit: 2893
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