DETAILED ACTION
This Office Action is in response to an application that was filed on 04/18/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings Objections
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s):
The limitations “further comprising: a plurality of second heat transfer patterns provided on the second pad patterns, respectively” in claim 10 needs to be shown so as to enable the mapping to the limitation structure in independent claim 1.
The limitation phrases “first heat transfer patterns” and “second heat transfer patterns” in the limitations “a plurality of first heat transfer patterns provided on the plurality of first pad patterns; and a plurality of second heat transfer patterns provided on the plurality of second pad patter” in independent claim 11 needs to be shown TOGETHER in a drawing. The limitation phrases “first heat transfer patterns” and “second heat transfer patterns” should be shown together in drawings and NOT separate drawings so as to maintain the required RELATIONSHIP and AVOID GAPS between the limitation structures in the claim.
The limitation phrases “first protective layer” and “second protective layer” in the limitations “a first protective layer provided on the second insulating layer and exposing at least portions of the second pad patterns; and a second protective layer provided on the third insulating layer” in independent claim 20 needs to be shown TOGETHER in a drawing. The limitation phrases “first protective layer” and “second protective layer” should be shown together in drawings and NOT separate drawings so as to maintain the required RELATIONSHIP and AVOID GAPS between the limitation structures in the claim.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objections
The disclosure is objected to because of following errors:
The specification is objected to because of the claimed structures of “first heat transfer patterns” and “second heat transfer patterns” are NOT properly indicated TOGETHER to support independent claim 11 as detailed in the drawing objections.
The specification is objected to because of the claimed structures of “first protective layer” and “second protective layer” are NOT properly indicated TOGETHER to support independent claim 20 as detailed in the drawing objections.
Appropriate correction is required as well as no new matter should be entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 4, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo et al. (US20210267043A and Yoo hereinafter).
Regarding claim 1, Yoo discloses a semiconductor substrate (item 200 of Fig. 3 and ¶[0154] shows and indicates semiconductor substrate 200 {light emitting package 200}), comprising: a plurality of first pad patterns (item 221 of Fig. 3 and ¶[0154] shows and indicates a plurality first pad patterns 221 {first pad 221}); a first insulating layer having a first surface and a second surface opposite to each other, wherein the first insulating layer covers side surfaces of the plurality of first pad patterns such that lower surfaces of the first pad patterns are exposed by the second surface of the first insulating layer (items 211, 213, 212 of Fig. 3 and ¶[0156] shows and indicates first insulating layer 211 having first surface 211_213 {contact surfaces between insulating layers 211 and 213} and second surface 212_211 {contact surfaces between insulating layers 212 and 211} opposite to each other; where first insulating layer 211 covers the side surfaces of the plurality of first pad patterns 221 such that lower surfaces 221_212 {surface of first pad 221 facing insulating layer 212} of first pad patterns 221 are exposed by second surface 212_211 of first insulating layer 211), wherein the first insulating layer has first openings that expose at least portions of upper surfaces of the plurality of first pad patterns (item V1 of Fig. 3 and ¶[0167 & 0177] shows and indicates where first insulating layer 211 has first openings V1-opening {opening formed by via V1 opening hole} that expose at least portions of upper surfaces 221_211 {surface of first pad 221 facing insulating layer 211} of the plurality of first pad patterns 221); a plurality of redistribution wirings provided on the first surface of the first insulating layer, wherein the plurality of redistribution wirings are electrically connected to the plurality of first pad patterns through the first openings of the first insulating layer (item 223 of Fig. 3 and ¶[0167] shows and indicates the plurality of redistribution wirings 223 {third pad 223} provided on first surface 211_213 of first insulating layer 211; where the plurality of redistribution wirings 223 are electrically connected to the plurality of first pad patterns 221 through first openings V1-opening of first insulating layer 211); a second insulating layer covering the plurality of redistribution wirings, wherein the second insulating layer has second openings that expose at least portions of the plurality of redistribution wirings (items 213, V3 of Fig. 3 and ¶[0156 & 0177] shows and indicates second insulating layer 213 covering the plurality of redistribution wirings 223; where second insulating layer 213 has second openings V3-opening {opening formed by via V3 opening hole} that expose at least portions of the plurality of redistribution wirings 223); a plurality of second pad patterns provided on the second insulating layer, wherein the plurality of second pad patterns are electrically connected to the plurality of redistribution wirings through the second openings of the second insulating layer (item 224 of Fig. 3 and ¶[0167] shows and indicates a plurality of second pad patterns 224 {fourth pad 224} provided on second insulating layer 213; where the plurality of second pad patterns 224 are electrically connected to the plurality of redistribution wirings 224 through second openings V3-opening of second insulating layer 213); and a plurality of heat transfer patterns provided on the plurality of first pad patterns and not covered by the first insulating layer (item V2 of Fig. 3 and ¶[0177] shows and indicates a plurality of heat transfer patterns V2 {via V2} provided on the plurality of first pad patterns 221 and not covered by first insulating layer 211).
Regarding claim 2, Yoo discloses a semiconductor substrate, further comprising: a first protective layer provided on the second surface of the first insulating layer and exposing at least portions of the heat transfer patterns; and a second protective layer provided on the second insulating layer to expose at least portions of the second pad patterns (item 212 of Fig. 3 and ¶[0156 & 0199] shows and indicates first protective layer 212 {insulating layer 230} provided on second surface 212_211 of first insulating layer 211 and exposing at least portions of heat transfer patterns V2; where second protective layer 230-lower {lower protective layer 230} is provided on second insulating layer 213 to expose at least portions of second pad patterns 224).
Regarding claim 3, Yoo discloses a semiconductor substrate, further comprising: a third insulating layer provided on the second surface of the first insulating layer and having third openings that expose at least portions of the heat transfer patterns; and a plurality of second redistribution wirings provided on the third insulating layer and electrically connected to the heat transfer patterns through the third openings (items 212, V2, 221 of Fig. 3 and ¶[0156 & 0177] shows and indicates is further comprised of third insulating layer 212 provided on second surface 212_211 of first insulating layer 211 and having third openings V2-opening {opening formed by via V2 opening hole} that expose at least portions of heat transfer patterns V2; and the plurality of second redistribution wirings 222 {second pad 222} provided on third insulating layer 212 and electrically connected to heat transfer patterns V2 through third openings V2-opening).
Regarding claim 4, Yoo discloses a semiconductor substrate, further comprising: a plurality of third pad patterns provided on the plurality of second redistribution wirings; and a plurality of external connection bumps provided on the plurality of third pad patterns, respectively (items 280, 100 of Fig. 3 and ¶[0167 & 0173] shows and indicates is further comprised of third pad patterns 280 {connection part 280} provided on the plurality of second redistribution wirings 222 {first pad 221}; and the plurality of external connection bumps 100 {surface emitting laser element 100} provided on the plurality of third pad patterns 280, respectively).
Regarding claim 8, Yoo discloses a semiconductor substrate, wherein the heat transfer patterns transmit at least one of a data signal, a ground signal, or a power signal to the first pad patterns (Fig. 3 and ¶[0167 & 0177] shows and indicates where heat transfer patterns V2 transmits at least a power signal to first pad patterns 223).
Regarding claim 9, Yoo discloses a semiconductor substrate, wherein each of the heat transfer patterns includes at least one of a signal pattern, a land pattern, a ball pattern, or a dummy pattern (Fig. 3 and ¶[0167 & 0177] shows and indicates where heat transfer patterns V2 includes a signal pattern).
Claims 1, 2, 5, 8, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US20220328467A1 and Chen hereinafter).
Regarding claim 1, Chen discloses a semiconductor substrate (item 100 of Figs. 2-4 and ¶[0021] shows and indicates semiconductor substrate 100 {package component 100}), comprising: a plurality of first pad patterns (item 110A of Fig. 2 and ¶[0023] shows and indicates a plurality first pad patterns 110A {metallization/redistribution pattern layers 110A}); a first insulating layer having a first surface and a second surface opposite to each other, wherein the first insulating layer covers side surfaces of the plurality of first pad patterns such that lower surfaces of the first pad patterns are exposed by the second surface of the first insulating layer (items 108A, 108B, 106 of Figs. 2_7 and ¶[0023 & 0039] shows and indicates first insulating layer 108A {dielectric layers 108 labeled 108A, 108B, and 108C} having first surface 108A_108B {contact surfaces between dielectric layer 108A and dielectric layer 108B} and second surface 108A_106 {contact surfaces between dielectric layer 108A and dielectric layer 106} opposite to each other; where first insulating layer 108A covers the side surfaces of the plurality of first pad patterns 110A such that the lower surfaces of first pad patterns 110A are exposed by second surface 108A_106 of first insulating layer 108A), wherein the first insulating layer has first openings that expose at least portions of upper surfaces of the plurality of first pad patterns (items 108A, 108B, 106 of Figs. 2_7 and ¶[0023] shows and indicates first insulating layer 108A has first openings 110A_110B {via formed between metallization/redistribution pattern layers 110A & 110B} that expose at least portions of the upper surfaces of the plurality of first pad patterns 110A); a plurality of redistribution wirings provided on the first surface of the first insulating layer, wherein the plurality of redistribution wirings are electrically connected to the plurality of first pad patterns through the first openings of the first insulating layer (item 110B of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates the plurality of redistribution wirings 110B {metallization/redistribution pattern layers 110B} provided on first surface 108A_108B of first insulating layer 108A; where the plurality of redistribution wirings 110B are electrically connected to the plurality of first pad patterns 110A through first openings 110A_110B of first insulating layer 108A); a second insulating layer covering the plurality of redistribution wirings, wherein the second insulating layer has second openings that expose at least portions of the plurality of redistribution wirings (items 108B, 110B, 110C of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates second insulating layer 108B {dielectric layer 108B} covering the plurality of redistribution wirings 110B; where second insulating layer 108B has second openings 110B_110C {via formed between metallization/redistribution pattern layers 110B & 110C} that expose at least portions of the plurality of redistribution wirings 110B); a plurality of second pad patterns provided on the second insulating layer, wherein the plurality of second pad patterns are electrically connected to the plurality of redistribution wirings through the second openings of the second insulating layer (item 110C of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates a plurality of second pad patterns 110C {metallization/redistribution pattern layers 110C} provided on second insulating layer 108B; where the plurality of second pad patterns 110C are electrically connected to the plurality of redistribution wirings 110B through second openings 110B_110C of second insulating layer 108B); and a plurality of heat transfer patterns provided on the plurality of first pad patterns and not covered by the first insulating layer (item 122 of Fig. 7 & Fig. 2 and ¶[0039] shows and indicates a plurality of heat transfer patterns 122 {under bump metallizations [UBMs] 122} provided on the plurality of first pad patterns 110A and not covered by first insulating layer 108A).
Regarding claim 2, Chen discloses a semiconductor substrate, further comprising: a first protective layer provided on the second surface of the first insulating layer and exposing at least portions of the heat transfer patterns; and a second protective layer provided on the second insulating layer to expose at least portions of the second pad patterns (items 106, 108C of Fig. 7 & Fig. 2 and ¶[0023 & 0039] shows and indicates is further comprised of first protective layer 106 {dielectric layer 106} provided on second surface 108A_106 of first insulating layer 108A and exposing at least portions of heat transfer patterns 122; where second protective layer 108C {dielectric layers 108C} provided on second insulating layer 108B to expose at least portions of second pad patterns 110C).
Regarding claim 5, Chen discloses a semiconductor substrate, wherein each of the plurality of first pad patterns has a first width, and each of the plurality of heat transfer patterns has a second width that is smaller than the first width (Fig. 2_7 & Fig. 2 and ¶[0023 & 0039] is interpolated to show where each of the plurality of first pad patterns 110A has a first width, and each of the plurality of heat transfer patterns 122 has a second width that is smaller than the first width).
Regarding claim 8, Chen discloses a semiconductor substrate, wherein the heat transfer patterns transmit at least one of a data signal, a ground signal, or a power signal to the first pad patterns (Figs. 2_7 and ¶[0023 & 0039] shows and indicates where heat transfer patterns 122 transmits at least a power signal to first pad patterns 110A).
Regarding claim 9, Chen discloses a semiconductor substrate, wherein each of the heat transfer patterns includes at least one of a signal pattern, a land pattern, a ball pattern, or a dummy pattern (Figs. 2_7 and ¶[0023 & 0039] shows and indicates where heat transfer patterns 122 includes a ball pattern).
Regarding claim 10, Chen discloses a semiconductor substrate, further comprising: a plurality of second heat transfer patterns provided on the second pad patterns, respectively (item 114 of Fig.4 & Figs. 2_7 and ¶[0030] shows and indicates the plurality of second heat transfer patterns 114 {bonding pads 114} provided on the plurality of second pad patterns 110C).
Claims 11, 12, 15, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen.
Regarding claim 11, Chen discloses a semiconductor substrate (item 100 of Figs. 2-4 and ¶[0021] shows and indicates semiconductor substrate 100 {package component 100}), comprising: a plurality of first pad patterns (item 110A of Fig. 2 and ¶[0023] shows and indicates a plurality first pad patterns 110A {metallization/redistribution pattern layers 110A}); a first insulating layer covering the plurality of first pad patterns, wherein the first insulating layer has first openings that expose at least portions of upper surfaces of the plurality of first pad patterns (items 108A, 110A, 110B of Figs. 2_7 and ¶[0023 & 0039] shows and indicates first insulating layer 108A {dielectric layers 108 labeled 108A, 108B, and 108C} covering the plurality of first pad patterns 110A; where first insulating layer 108A has first openings 110A_110B {via formed between metallization/redistribution pattern layers 110A & 110B} that expose at least portions of upper surfaces of the plurality of first pad patterns 110A); a plurality of redistribution wirings provided on an upper surface of the first insulating layer, wherein the plurality of redistribution wirings are electrically connected to the plurality of first pad patterns through the first openings of the first insulating layer (item 110B of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates the plurality of redistribution wirings 110B {metallization/redistribution pattern layers 110B} provided on upper surface 108A_108B {contact surfaces between dielectric layer 108A and dielectric layer 108B} of first insulating layer 108A; where the plurality of redistribution wirings 110B are electrically connected to the plurality of first pad patterns 110A through first openings 110A_110B of first insulating layer 108A); a second insulating layer provided on the first insulating layer, wherein the second insulating layer covers the plurality of redistribution wirings, wherein the second insulating layer has second openings that expose at least portions of the plurality of redistribution wirings (items 108B, 110B, 110C of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates second insulating layer 108B {dielectric layer 108B} covering the plurality of redistribution wirings 110B; where second insulating layer 108B has second openings 110B_110C {via formed between metallization/redistribution pattern layers 110B & 110C} that expose at least portions of the plurality of redistribution wirings 110B); a plurality of second pad patterns provided on the second insulating layer, wherein the plurality of second pad patterns are electrically connected to the plurality of redistribution wirings through the second openings of the second insulating layer (item 110C of Fig. 2 & Fig. 7 and ¶[0023] shows and indicates a plurality of second pad patterns 110C {metallization/redistribution pattern layers 110C} provided on second insulating layer 108B; where the plurality of second pad patterns 110C are electrically connected to the plurality of redistribution wirings 110B through second openings 110B_110C of second insulating layer 108B); a plurality of first heat transfer patterns provided on the plurality of first pad patterns (item 122 of Fig. 7 & Fig. 2 and ¶[0039] shows and indicates a plurality of heat transfer patterns 122 {under bump metallizations [UBMs] 122} provided on the plurality of first pad patterns 110A); and a plurality of second heat transfer patterns provided on the plurality of second pad patter (item 114 of Fig.4 & Figs. 2_7 and ¶[0030] shows and indicates the plurality of second heat transfer patterns 114 {bonding pads 114} provided on the plurality of second pad patterns 110C).
Regarding claim 12, Chen discloses a semiconductor substrate, further comprising: a first protective layer provided on a lower surface of the first insulating layer and exposing at least portions of the plurality of first heat transfer patterns; and a second protective layer provided on an upper surface the second insulating layer to expose at least portions of the plurality of second heat transfer patterns (items 106, 108C of Fig. 7 & Fig. 2 and ¶[0023 & 0039] shows and indicates is further comprised of first protective layer 106 {dielectric layer 106} provided on lower surface 108A_106 of first insulating layer 108A and exposing at least portions of first heat transfer patterns 122; where second protective layer 108C {dielectric layers 108C} provided on the upper surface second insulating layer 108B to expose at least portions of second heat transfer patterns 114).
Regarding claim 15, Chen discloses a semiconductor substrate, wherein each of the plurality of first pad patterns has a first width, and each of the plurality of heat transfer patterns has a second width that is smaller than the first width (Fig. 2_7 & Fig. 2 and ¶[0023 & 0039] is interpolated to show where each of the plurality of first pad patterns 110A has a first width, and each of the plurality of heat transfer patterns 122 has a second width that is smaller than the first width).
Regarding claim 18, Chen discloses a semiconductor substrate, wherein the heat transfer patterns transmit at least one of a data signal, a ground signal, or a power signal to the first pad patterns (Figs. 2_7 and ¶[0023 & 0039] shows and indicates where heat transfer patterns 122 transmits at least a power signal to first pad patterns 110A).
Regarding claim 19, Chen discloses a semiconductor substrate, wherein each of the heat transfer patterns includes at least one of a signal pattern, a land pattern, a ball pattern, or a dummy pattern (Figs. 2_7 and ¶[0023 & 0039] shows and indicates where heat transfer patterns 122 includes a ball pattern).
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo.
Regarding claim 20, Yoo discloses a semiconductor substrate (item 200 of Fig. 3 and ¶[0154] shows and indicates semiconductor substrate 200 {light emitting package 200}), comprising: a plurality of first pad patterns (item 221 of Fig. 3 and ¶[0154] shows and indicates a plurality first pad patterns 221 {first pad 221}); a first insulating layer having a first surface and a second surface opposite to each other, wherein the first insulating layer covers side surfaces of the plurality of first pad patterns such that lower surfaces of the plurality of first pad patterns are exposed from the second surface of the first insulating layer (items 211, 213, 212 of Fig. 3 and ¶[0156] shows and indicates first insulating layer 211 having first surface 211_213 {contact surfaces between insulating layers 211 and 213} and second surface 212_211 {contact surfaces between insulating layers 212 and 211} opposite to each other; where first insulating layer 211 covers the side surfaces of the plurality of first pad patterns 221 such that lower surfaces 221_212 {surface of first pad 221 facing insulating layer 212} of first pad patterns 221 are exposed by second surface 212_211 of first insulating layer 211), wherein the first insulating layer has first openings that expose at least portions of upper surfaces of the plurality of first pad patterns (item V1 of Fig. 3 and ¶[0167 & 0177] shows and indicates where first insulating layer 211 has first openings V1-opening {opening formed by via V1 opening hole} that expose at least portions of upper surfaces 221_211 {surface of first pad 221 facing insulating layer 211} of the plurality of first pad patterns 221); a plurality of redistribution wirings provided on the first surface of the first insulating layer, wherein the plurality of redistribution wirings are electrically connected to the first pad patterns through the first openings of the first insulating layer (item 223 of Fig. 3 and ¶[0167] shows and indicates the plurality of redistribution wirings 223 {third pad 223} provided on first surface 211_213 of first insulating layer 211; where the plurality of redistribution wirings 223 are electrically connected to the plurality of first pad patterns 221 through first openings V1-opening of first insulating layer 211); a second insulating layer covering the plurality of redistribution wirings and having second openings that expose at least portions of the plurality of redistribution wirings (items 213, V3 of Fig. 3 and ¶[0156 & 0177] shows and indicates second insulating layer 213 covering the plurality of redistribution wirings 223; where second insulating layer 213 has second openings V3-opening {opening formed by via V3 opening hole} that expose at least portions of the plurality of redistribution wirings 223); a plurality of second pad patterns provided on the second insulating layer, wherein the plurality of second pad patterns are electrically connected to the plurality of redistribution wirings through the second openings of the second insulating layer (item 224 of Fig. 3 and ¶[0167] shows and indicates a plurality of second pad patterns 224 {fourth pad 224} provided on second insulating layer 213; where the plurality of second pad patterns 224 are electrically connected to the plurality of redistribution wirings 224 through second openings V3-opening of second insulating layer 213); a plurality of heat transfer patterns provided on the lower surfaces of the plurality of first pad patterns and protruding beyond the second surface of the first insulating layer (item V2 of Fig. 3 and ¶[0177] shows and indicates a plurality of heat transfer patterns V2 {via V2} provided on the lower surfaces 221_212 of the plurality of first pad patterns 221 and protruding beyond second surface 212_211 of first insulating layer 211); a third insulating layer provided on the second surface of the first insulating layer and having third openings that expose at least portions of the heat transfer patterns (items 212, V2 of Fig. 3 and ¶[0156 & 0177] shows and indicates third insulating layer 212 provided on second surface 212_211 of first insulating layer 211 and having third openings V2-opening {opening formed by via V2 opening hole} that expose at least portions of heat transfer patterns V2); a plurality of second redistribution wirings provided on the third insulating layer and electrically connected to the heat transfer patterns through the third openings of the third insulating layer (item 222 of Fig. 3 and ¶[0167] shows and indicates second redistribution wirings 222 {second pad 222} provided on third insulating layer 212 and electrically connected to heat transfer patterns V2 through third openings V2-opening of third insulating layer 212); a first protective layer provided on the second insulating layer and exposing at least portions of the second pad patterns; and a second protective layer provided on the third insulating layer (item 230 of Fig. 3 and ¶[0199] shows and indicates first protective layer 230-lower {lower protective layer 230} provided on second insulating layer 213 and exposing at least portions of second pad patterns 224; and where second protective layer 230-upper {upper protective layer 230} is provided on third insulating layer 212).
Allowable Subject Matter
Claims 6-7, 13-14, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the primary reason for allowance is due to a semiconductor substrate, wherein a difference between the first width and the second width is within a range of about 3 μm to about 5 μm.
Regarding claim 7, the primary reason for allowance is due to a semiconductor substrate, wherein each of the first pad patterns has a first thickness, wherein each of the heat transfer patterns has a second thickness, wherein the first thickness is within a range of about 10 μm to about 20 μm, and the second thickness is within a range of about 10 μm to about 20 μm.
Regarding claim 13, the primary reason for allowance is due to a semiconductor substrate, further comprising: a third insulating layer provided on a lower surface of the first insulating layer and having third openings that expose at least portions of the first heat transfer patterns; and a plurality of second redistribution wirings provided on the third insulating layer and electrically connected to the first heat transfer patterns through the third openings.
Regarding claim 14, the primary reason for allowance is due to dependency on claim 13.
Regarding claim 16, the primary reason for allowance is due to a semiconductor substrate, wherein a difference between the first width and the second width is within a range of about 3 μm to about 5 μm.
Regarding claim 17, the primary reason for allowance is due to a semiconductor substrate, wherein each of the first pad patterns has a first thickness, wherein each of the heat transfer patterns has a second thickness, wherein the first thickness is within a range of about 10 μm to about 20 μm, and the second thickness is within a range of about 10 μm to about 20 μm.
Conclusion
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847