DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are presented for examination.
Claim Objections
Claim 5 is objected to because of the following informalities: in line 1, "comprises" should be amended to read -comprising-. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 10-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (US 2024/0266256 and Lee hereinafter).
As to claims 1-8 and 10-17: Lee discloses [claim 1] a semiconductor device (Figs. 4, 5A, and 5B; [0038]) comprising: a transistor (Figs. 4, 5A, 5B, and 5D; NR1; [0040]) located in a first device area (area in which NR1 is formed) and comprising a gate structure (leftmost structure comprising CH2, GE, and GI; [0065]), a first source/drain region (leftmost SD2 that is connected to AC; [0047]) located on a first side (left side) of the gate structure (leftmost structure comprising CH2, GE, and GI) and a second source/drain region (2nd from the left SD2 that is connected to BSC2; [0047]) located on a second side (right side) of the gate structure (leftmost structure comprising CH2, GE, and GI); a frontside source/drain contact structure (Fig. 5B; leftmost AC; [0080]) contacting (AC is electrically connected to all parts of leftmost SD2) a topmost surface of the first source/drain region (leftmost SD2); a backside ballast resistor (Fig. 5B; comprising either the lower half of SEC or all of SEC; SEC is interpreted to be a backside ballast resistor as it is the same structure and material as the instant invention, specifically a doped semiconductor layer, and the SEC will operate as a backside ballast resistor; [0088] and [0091]) electrically contacting (SEC is electrically connected to all parts of leftmost SD2) a bottommost surface of the second source/drain region (2nd from the left SD1); and a backside source/drain contact structure (Fig. 5B; SC; [0088]) in contact with the backside ballast resistor (comprising either the lower half of SEC or all of SEC); [claim 2] further comprising a frontside back-end-of-the-line (BEOL) structure (Fig. 5B; comprising M1 and M2; [0095] and [0099]) in contact with the frontside source/drain contact structure (leftmost AC); [claim 3] further comprising a backside interconnect structure (Fig. 5B; comprising LIN and PCP; [0088]) in contact with the backside source/drain contact structure (SC); [claim 4] wherein the backside ballast resistor (Fig. 5B; comprising all of SEC) is in direct physical contact with the bottommost surface (as shown in the Figure) of the second source/drain region (SD2); [claim 5] further comprises a semiconductor layer (Fig. 5B; upper half of SEC) located between the backside ballast resistor (lower half of SEC; claim doesn’t state that the semiconductor layer and the backside ballast resistor comprise separate materials; therefore, Examiner interprets that they can comprise the same material, specifically that of SEC) and the bottommost surface (as shown in the Figure) of the second source/drain region (SD2); [claim 6] wherein the transistor is a nanosheet transistor (Fig. 5B; [0045]) and the nanosheet transistor is located on a frontside (top) of a bottom dielectric isolation layer (ESL; [0043]); [claim 7] wherein the first source/drain region (Fig. 5B; leftmost SD2) and the second source/drain region (2nd from the left SD2) are of a first conductivity type (can be n-type; [0047]), and the backside ballast resistor (comprising at least half of SEC) is of the first conductivity type (SEC connected to SD2 can comprise n-type dopants; [0092]); [claim 8] wherein the first conductivity type is n-type (SEC connected to SD2 can comprise n-type dopants; [0092]); [claim 10] wherein the backside ballast resistor (Fig. 5B; SEC) has an upper portion (the uppermost portion, the domed portion, of SEC) having a first width (width at the topmost part of the dome portion) and a lower portion (the portion of SEC having vertically straight sidewalls) having a second width, wherein the second width is greater than the first width (the portion of SEC with the vertically straight sidewalls has a horizontal width greater than at the domed portion of SEC); [claim 11] wherein the backside source/drain contact structure (Fig. 5D; SC) has a third width (width at the lowermost portion of SC that is pointed has a horizontal width less than that of the portion of SEC that has vertically straight sidewalls) that is less than the second width of the lower portion of the backside ballast resistor (the portion of SEC having vertically straight sidewalls); [claim 12] further comprising a backside interlayer dielectric (ILD) layer (Fig. 5D; 105 is interpreted to be a backside ILD as it is formed on the backside of the gate structure and can be a dielectric material; [0039]) embedding both the backside ballast resistor (SEC) and the backside source/drain contact structure (SC); [claim 13] further comprising a logic transistor (Fig. 4; PR1, NR1, PR2, and NR2 are logic transistors, the claimed transistor is interpreted to be PR1; [0022] and [0029]) located in a second device area (area in which PR1 is formed) that is adjacent to the first device area (area in which NR1 is formed); [claim 14] wherein a source/drain region (Fig. 5A; 2nd from the left SD1; [0046]) of the logic transistor (PR1) is in electrical contact with a logic side backside source/drain contact structure (SC connected to SD1; [0076]); [claim 15] further comprising a backside interlayer dielectric (ILD) layer (Fig. 5D; 105 is interpreted to be a backside ILD as it is formed on the backside of the gate structure and can be a dielectric material; [0039]) embedding each of the backside ballast resistor (SEC connected to SD2), the backside source/drain contact structure (SC connected to SD2) and the logic side backside source/drain contact structure (SC connected to SD1); [claim 16] further comprising a backside interconnect structure (Figs. 5A and 5B; PCP; [0088]) in contact with the backside source/drain contact structure (SC connected to SD2) and the logic side backside source/drain contact structure (SC connected to SD1); [claim 17] wherein the transistor (Fig. 4; NR1) and logic transistor (PR1) are both nanosheet transistors ([0045]), and each nanosheet transistor is located on a frontside (top) of a bottom dielectric isolation layer (ESL; [0043]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Lee discloses that the transistor is an n-type transistor (see Fig. 5B and [0047]).
Lee fails to expressly disclose wherein the first conductivity type is p-type.
However, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to switch the conductivity type of each of the semiconductor layers in the structure of Fig. 4 such that the n-type becomes p-type and p-type becomes n-type as the change would still result in CMOS structures used in a logic device with enhanced electrical properties ([0005]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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