DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 19, 2026.
Claims 1-20 are pending. Claims 1, 8 and 14 are amended. Claims 1, 8 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on February 19, 2026. These drawings are unacceptable.
All of the Figures filed on February 19, 2026 and April 18, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in grayscale. The defect is most easily observable on Patent Center (and Docket Application Viewer, DAV) when increasing zoom to 300%. The lettering and features intended to be solid black, instead have regular patterns of white dots. See the following Examiner Markup Application’s Figure 6.
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The degraded quality, and the basis of the objection to the Drawings, is the Figures are not in solid black, but have features in shades of gray that caused pixelated. Here is a snapshot from recently filed PDF (not from the DRW Drawings of Record). The lettering for “FIG. 3A” of Figure 3A is in color code #221E1F, which is a very dark gray.
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The color codes #221E1F is 24-bit color codes expressed in hexadecimal format of #RRGGBB. A website that explains 24-bit color codes is here: RGB Color Codes Chart (https://www.rapidtables.com/web/color/RGB_Color.html). When viewing 24-bit images, what may appear on screen as black may not actually be black. Black is #000000. #221E1F is a very dark gray, but not black.
Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20190147959) in view of Dunga et al. (US 20140112075).
Regarding independent claim 1, Hsu discloses a memory apparatus [Fig. 3], comprising:
memory cells connected to one of a plurality of word lines [see Fig. 16, para. 109-110], comprised a plurality of strings [see Fig. 16, each page group contains multiple cell strings, such as string 1601, para. 109] and configured to retain a threshold voltage corresponding to data states [para. 117]; and
a control [Fig. 16: 1608, para. 111] means configured to:
apply one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation [see Fig. 18: step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V, while addressing multiple page groups, para. 120-122. Page group 1600a comprises multiple pages of which PAGE 0 is defined across the multiple cell strings in page group 1600a, page group 1600b comprises multiple pages of which PAGE 1 is defined across the multiple cell strings in page group 1600b, see Fig. 16, para. 109. Hsu also defines a ‘program pulse’ means the voltages on the word lines are maintained for a certain programming time (Tpgm), such as 10 µs to 30 µs, then the word line voltages are discharged, para. 117], and
selectively program the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage [see Fig. 18, in step 1801c, the data 1803a for the page (PAGE 0) is applied to the bit lines (BL[0:k]) and the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zero.sup.th) page group, para. 122. After PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] without actively ramping voltages on the plurality of word lines down and up between programming of the first one and the at least one subsequent one of the plurality of strings [Hsu discloses preform operations of repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation, para. 9. See Fig. 18, Vpgm applied to word line remains unchanged while programming two strings].
However, Hsu is silent with respect to disclose memory cells are disposed in memory holes arranged in rows.
Dunga et al. teach memory cells are disposed in memory holes arranged in rows [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND stack with vertical memory holes forming the strings as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
Regarding claim 2, Hsu in combination with Dunga et al. teach the limitations with respect to claim 1.
Furthermore, Hsu discloses the plurality of word lines [see Fig. 16: WL[0]-WL[m]], the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes [see Fig. 16, the string 1601 is connected to bit line (BL[0]) and includes a drain select gate (DSG) 1602, a source select gate (SSG) 1603, and multiple NAND flash memory cells 1604a-e connected serially, para. 109], the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines [see Fig. 16, a drain select gate (DSG) 1602 is connected to the bit line BL[0], para. 109-110] and the source-side select gate transistor of each of the memory holes is connected to a source line [see Fig. 16, the source select gates (e.g., SSG 1603) are connected to a source line (SL) control signal, para. 110], and the control means is further configured to:
apply a gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings [see Fig. 18, the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zeroth) page group, para. 122] while applying one of a steady state voltage and an inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the first one of the plurality of strings to allow the programming of the memory cells of the first one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122], the gate transistor voltage selected to allow the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to conduct [see Fig. 18, in a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119]; and
apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] while applying one of the steady state voltage and the inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the at least one subsequent one of the plurality of strings to allow the programming of the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122].
However, Hsu is silent with respect to disclose a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack.
Dunga et al. teach a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack [see Fig. 3A: D3-D5, para. 52], the memory holes extend vertically through the stack [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND comprising a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
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Regarding claim 3, Hsu in combination with Dunga et al. teach the limitations with respect to claim 2.
Furthermore, Hsu discloses the initial program stage includes a first period and a second period and a third period [see Examiner Markup Hsu’s Figure 18: PC1, PC2, PC3], and the control means is further configured to:
apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while applying the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings during the first period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC1, in step 1801c, the select gate SG[0] is pulsed to load VDD into all the channels of all the cell strings in the page 0 while the select gate SG[1] associated with the page 1 is turned off, para. 122];
apply the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to the steady state voltage during the second period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC2, in step 1801c, after PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off and the select gate SG[1] associated with the page 1 is also turned off in this time period, para. 124]; and
apply the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the third period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC3, in step 1801c, the select gate SG[1] associated with the page 1 is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, while the select gate SG[0] associated with the page 0 is turned off, para. 124].
However, Hsu just discloses in a second step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V while all the unselected word lines (such as WL[1:c−1] through WL[c+1:m] for example) are supplied with a middle-high inhibit voltage (Vinh), such as 8V to 10V, para. 120. Hsu is silent with respect to wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage.
Dunga et al. teach wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage [see Fig. 8D, WL_sel and WL_unsel increase from an initial level such as 0 V to a pass voltage level (Vpass) at t4-t5, para. 96] and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, at t6, WL_sel increases from Vpass to Vpgm, while WL_unsel remains at Vpass, para. 96] and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, WL_sel remains at Vpgm, while WL_unsel remains at Vpass from t7-t8].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming is executed with a boost stage, an initial program stage and a subsequent program stage as taught by Dunga et al. to reduce program disturb and improve programming reliability [see Dunga et al.’s para. 80].
Regarding claim 4, Hsu in combination with Dunga et al. teach the limitations with respect to claim 3.
Furthermore, Hsu discloses wherein data of the memory cells comprises one bit per each of the memory cells and the data states include, in order of the threshold voltage increasing, an erased data state and a programmed data state [para. 72 as well as para. 122], and the control means is further configured to:
maintain voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings as the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [see Fig. 18, the bit lines for programming are applied with 0V, para. 71, thus when a memory cell is programmed in first period, the bit line coupled to that memory cell remains at 0V during the second period and the third period of the initial program stage];
ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings to the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71, thus, when a memory cell is programmed during the first period, and after that is set for erasing, the bit line coupled to that memory cell is applied with 0V during the first period and applied with VDD during the second period and the third period of the initial program stage];
ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings to the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period and the second period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71. In a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), para. 119; thus, when a memory cell is programmed during the third period, the bit line coupled to that memory cell is applied with VDD during the first period and second period, after that it is applied with 0V during the third period]; and
maintain voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings as the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71; thus, when a memory cell is set for erasing, the bit line coupled to that memory cell remains at VDD for inhibiting].
Regarding claim 5, Hsu in combination with Dunga et al. teach the limitations with respect to claim 3.
Furthermore, Hsu discloses a duration of the first period of the initial program stage is adjustable, the first period of the initial program stage being shorter than the at least one subsequent program stage [see Examiner Markup Hsu’s Figure 18, during an MPS operation, loading multiple page buffers' data to multiple blocks generally takes 1 or less than 1 μs. Compared with 30 μs program pulse, loading time from page buffer to blocks is small, para. 77].
Regarding claim 6, Hsu in combination with Dunga et al. teach the limitations with respect to claim 3.
Furthermore, Hsu discloses wherein the control means is further configured to ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells of the at least one subsequent one of the plurality of strings from one of the steady state voltage and the inhibiting voltage to another of the steady state voltage and the inhibiting voltage before ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the initial program stage [see Fig. 18, in a first step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1) from 0V, para. 119].
Regarding claim 7, Hsu in combination with Dunga et al. teach the limitations with respect to claim 3.
Furthermore, Hsu discloses wherein the boost stage includes, in sequence, a first ending period and a second ending period and a third ending period, and the control means is further configured to apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings during the boost stage to leak a boost potential of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings, the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings ramped back down to the steady state voltage during the first ending period of the boost stage [see Fig. 18, in a first step 1801a, all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, as shown in 1802a through 1802b, para. 119].
Regarding independent claim 8, Hsu discloses a controller [Fig. 16: 1608, para. 111] in communication with a memory apparatus including memory cells connected to one of a plurality of word lines [see Fig. 16, para. 109-110], comprised a plurality of strings [see Fig. 16, each page group contains multiple cell strings, such as string 1601, para. 109] and configured to retain a threshold voltage corresponding to data states [para. 117], the controller configured to:
instruct the memory apparatus to apply one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation [see Fig. 18: step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V, while addressing multiple page groups, para. 120-122. Page group 1600a comprises multiple pages of which PAGE 0 is defined across the multiple cell strings in page group 1600a, page group 1600b comprises multiple pages of which PAGE 1 is defined across the multiple cell strings in page group 1600b, see Fig. 16, para. 109. Hsu also defines a ‘program pulse’ means the voltages on the word lines are maintained for a certain programming time (Tpgm), such as 10 µs to 30 µs, then the word line voltages are discharged, para. 117]; and
instruct the memory apparatus to selectively program the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage [see Fig. 18, in step 1801c, the data 1803a for the page (PAGE 0) is applied to the bit lines (BL[0:k]) and the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zero.sup.th) page group, para. 122. After PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] without actively ramping voltages on the plurality of word lines down and up between programming of the first one and the at least one subsequent one of the plurality of strings [Hsu discloses preform operations of repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation, para. 9. See Fig. 18, Vpgm applied to word line remains unchanged while programming two strings].
However, Hsu is silent with respect to disclose memory cells are disposed in memory holes arranged in rows.
Dunga et al. teach memory cells are disposed in memory holes arranged in rows [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND stack with vertical memory holes forming the strings as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
Regarding claim 9, Hsu in combination with Dunga et al. teach the limitations with respect to claim 8.
Furthermore, Hsu discloses the plurality of word lines [see Fig. 16: WL[0]-WL[m]], the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes [see Fig. 16, the string 1601 is connected to bit line (BL[0]) and includes a drain select gate (DSG) 1602, a source select gate (SSG) 1603, and multiple NAND flash memory cells 1604a-e connected serially, para. 109], the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines [see Fig. 16, a drain select gate (DSG) 1602 is connected to the bit line BL[0], para. 109-110] and the source-side select gate transistor of each of the memory holes is connected to a source line [see Fig. 16, the source select gates (e.g., SSG 1603) are connected to a source line (SL) control signal, para. 110], and the controller is further configured to:
instruct the memory apparatus to apply a gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings [see Fig. 18, the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zeroth) page group, para. 122] while applying one of a steady state voltage and an inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the first one of the plurality of strings to allow the programming of the memory cells of the first one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122], the gate transistor voltage selected to allow the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to conduct [see Fig. 18, in a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119]; and
instruct the memory apparatus to apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] while applying one of the steady state voltage and the inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the at least one subsequent one of the plurality of strings to allow the programming of the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122].
However, Hsu is silent with respect to disclose a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack.
Dunga et al. teach a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack [see Fig. 3A: D3-D5, para. 52], the memory holes extend vertically through the stack [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND comprising a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
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Regarding claim 10, Hsu in combination with Dunga et al. teach the limitations with respect to claim 9.
Furthermore, Hsu discloses the initial program stage includes a first period and a second period and a third period [see Examiner Markup Hsu’s Figure 18: PC1, PC2, PC3], and the controller is further configured to:
instruct the memory apparatus to apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while applying the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings during the first period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC1, in step 1801c, the select gate SG[0] is pulsed to load VDD into all the channels of all the cell strings in the page 0 while the select gate SG[1] associated with the page 1 is turned off, para. 122];
instruct the memory apparatus to apply the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to the steady state voltage during the second period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC2, in step 1801c, after PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off and the select gate SG[1] associated with the page 1 is also turned off in this time period, para. 124]; and
instruct the memory apparatus to apply the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the third period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC3, in step 1801c, the select gate SG[1] associated with the page 1 is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, while the select gate SG[0] associated with the page 0 is turned off, para. 124].
However, Hsu just discloses in a second step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V while all the unselected word lines (such as WL[1:c−1] through WL[c+1:m] for example) are supplied with a middle-high inhibit voltage (Vinh), such as 8V to 10V, para. 120. Hsu is silent with respect to wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage.
Dunga et al. teach wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage [see Fig. 8D, WL_sel and WL_unsel increase from an initial level such as 0 V to a pass voltage level (Vpass) at t4-t5, para. 96] and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, at t6, WL_sel increases from Vpass to Vpgm, while WL_unsel remains at Vpass, para. 96] and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, WL_sel remains at Vpgm, while WL_unsel remains at Vpass from t7-t8].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming is executed with a boost stage, an initial program stage and a subsequent program stage as taught by Dunga et al. to reduce program disturb and improve programming reliability [see Dunga et al.’s para. 80].
Regarding claim 11, Hsu in combination with Dunga et al. teach the limitations with respect to claim 10.
Furthermore, Hsu discloses wherein data of the memory cells comprises one bit per each of the memory cells and the data states include, in order of the threshold voltage increasing, an erased data state and a programmed data state [para. 72 as well as para. 122], and the controller is further configured to:
instruct the memory apparatus to maintain voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings as the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [see Fig. 18, the bit lines for programming are applied with 0V, para. 71, thus when a memory cell is programmed in first period, the bit line coupled to that memory cell remains at 0V during the second period and the third period of the initial program stage];
instruct the memory apparatus to ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings to the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71, thus, when a memory cell is programmed during the first period, and after that is set for erasing, the bit line coupled to that memory cell is applied with 0V during the first period and applied with VDD during the second period and the third period of the initial program stage];
instruct the memory apparatus to ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings to the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period and the second period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71. In a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), para. 119; thus, when a memory cell is programmed during the third period, the bit line coupled to that memory cell is applied with VDD during the first period and second period, after that it is applied with 0V during the third period]; and
instruct the memory apparatus to maintain voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings as the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71; thus, when a memory cell is set for erasing, the bit line coupled to that memory cell remains at VDD for inhibiting].
Regarding claim 12, Hsu in combination with Dunga et al. teach the limitations with respect to claim 10.
Furthermore, Hsu discloses a duration of the first period of the initial program stage is adjustable, the first period of the initial program stage being shorter than the at least one subsequent program stage [see Examiner Markup Hsu’s Figure 18, during an MPS operation, loading multiple page buffers' data to multiple blocks generally takes 1 or less than 1 μs. Compared with 30 μs program pulse, loading time from page buffer to blocks is small, para. 77].
Regarding claim 13, Hsu in combination with Dunga et al. teach the limitations with respect to claim 10.
Furthermore, Hsu discloses wherein the control is further configured to ramp voltage applied to ones of the plurality of bit lines coupled to the memory cells of the at least one subsequent one of the plurality of strings from one of the steady state voltage and the inhibiting voltage to another of the steady state voltage and the inhibiting voltage before ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the initial program stage [see Fig. 18, in a first step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1) from 0V, para. 119].
Regarding independent claim 14, Hsu discloses a method of operating a memory apparatus including memory cells connected to one of a plurality of word lines [see Fig. 16, para. 109-110], comprised a plurality of strings [see Fig. 16, each page group contains multiple cell strings, such as string 1601, para. 109] and configured to retain a threshold voltage corresponding to data states [para. 117], the method comprising the steps of:
applying one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation [see Fig. 18: step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V, while addressing multiple page groups, para. 120-122. Page group 1600a comprises multiple pages of which PAGE 0 is defined across the multiple cell strings in page group 1600a, page group 1600b comprises multiple pages of which PAGE 1 is defined across the multiple cell strings in page group 1600b, see Fig. 16, para. 109. Hsu also defines a ‘program pulse’ means the voltages on the word lines are maintained for a certain programming time (Tpgm), such as 10 µs to 30 µs, then the word line voltages are discharged, para. 117], and
selectively programming the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage [see Fig. 18, in step 1801c, the data 1803a for the page (PAGE 0) is applied to the bit lines (BL[0:k]) and the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zero.sup.th) page group, para. 122. After PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] without actively ramping voltages on the plurality of word lines down and up between programming of the first one and the at least one subsequent one of the plurality of strings [Hsu discloses preform operations of repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation, para. 9. See Fig. 18, Vpgm applied to word line remains unchanged while programming two strings].
However, Hsu is silent with respect to disclose memory cells are disposed in memory holes arranged in rows.
Dunga et al. teach memory cells are disposed in memory holes arranged in rows [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND stack with vertical memory holes forming the strings as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
Regarding claim 15, Hsu in combination with Dunga et al. teach the limitations with respect to claim 14.
Furthermore, Hsu discloses the plurality of word lines [see Fig. 16: WL[0]-WL[m]], the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes [see Fig. 16, the string 1601 is connected to bit line (BL[0]) and includes a drain select gate (DSG) 1602, a source select gate (SSG) 1603, and multiple NAND flash memory cells 1604a-e connected serially, para. 109], the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines [see Fig. 16, a drain select gate (DSG) 1602 is connected to the bit line BL[0], para. 109-110] and the source-side select gate transistor of each of the memory holes is connected to a source line [see Fig. 16, the source select gates (e.g., SSG 1603) are connected to a source line (SL) control signal, para. 110], and the method further includes the steps of:
applying a gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings [see Fig. 18, the first select gate (SG[0] associated with the page group 0) is pulsed to load the data into the channels (Channel 0 [0:k]) of the cell strings of the selected (zeroth) page group, para. 122] while applying one of a steady state voltage and an inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the first one of the plurality of strings to allow the programming of the memory cells of the first one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122], the gate transistor voltage selected to allow the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to conduct [see Fig. 18, in a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119]; and
applying the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124] while applying one of the steady state voltage and the inhibiting voltage to ones of the plurality of bit lines coupled to the memory holes of the at least one subsequent one of the plurality of strings to allow the programming of the memory cells of the at least one subsequent one of the plurality of strings [see Fig. 18, the bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, as shown at 1804a. The bit lines with VDD (data 1) will not discharge the channels of the associated strings, due to the select gate being reverse-biased, thus these cell string channels will remain at the inhibit voltage (Vch), as shown at 1804b, para. 122].
However, Hsu is silent with respect to disclose a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack.
Dunga et al. teach a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack [see Fig. 3A: D3-D5, para. 52], the memory holes extend vertically through the stack [see Fig. 2A, para. 40].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming runs on a 3D NAND comprising a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack as taught by Dunga et al. to realize the Bit Cost Scalable (BiCS) structure that provides ultra-high density and simultaneously defines many memory layers with the conductive layers serving as the control gates [see Dunga et al.’s para. 4].
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Regarding claim 16, Hsu in combination with Dunga et al. teach the limitations with respect to claim 15.
Furthermore, Hsu discloses the initial program stage includes a first period and a second period and a third period [see Examiner Markup Hsu’s Figure 18: PC1, PC2, PC3], and the method further includes the steps of:
applying the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while applying the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings during the first period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC1, in step 1801c, the select gate SG[0] is pulsed to load VDD into all the channels of all the cell strings in the page 0 while the select gate SG[1] associated with the page 1 is turned off, para. 122];
applying the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings to the steady state voltage during the second period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC2, in step 1801c, after PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off and the select gate SG[1] associated with the page 1 is also turned off in this time period, para. 124]; and
applying the steady state voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the first one of the plurality of strings while ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the third period of the initial program stage [see Examiner Markup Hsu’s Figure 18: PC3, in step 1801c, the select gate SG[1] associated with the page 1 is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, while the select gate SG[0] associated with the page 0 is turned off, para. 124].
However, Hsu just discloses in a second step 1801b, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V while all the unselected word lines (such as WL[1:c−1] through WL[c+1:m] for example) are supplied with a middle-high inhibit voltage (Vinh), such as 8V to 10V, para. 120. Hsu is silent with respect to wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage.
Dunga et al. teach wherein the program operation includes, in sequential order, a boost stage in which selected ones of the plurality of word lines and unselected ones of the plurality of word lines ramp up to a pass voltage [see Fig. 8D, WL_sel and WL_unsel increase from an initial level such as 0 V to a pass voltage level (Vpass) at t4-t5, para. 96] and an initial program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, at t6, WL_sel increases from Vpass to Vpgm, while WL_unsel remains at Vpass, para. 96] and at least one subsequent program stage in which the selected ones of the plurality of word lines ramp to the program voltage and the unselected ones of the plurality of word lines remain at the pass voltage [see Fig. 8D, WL_sel remains at Vpgm, while WL_unsel remains at Vpass from t7-t8].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dunga et al. to the teachings of Hsu such that Hsu’s multiple page programming is executed with a boost stage, an initial program stage and a subsequent program stage as taught by Dunga et al. to reduce program disturb and improve programming reliability [see Dunga et al.’s para. 80].
Regarding claim 17, Hsu in combination with Dunga et al. teach the limitations with respect to claim 16.
Furthermore, Hsu discloses wherein data of the memory cells comprises one bit per each of the memory cells and the data states include, in order of the threshold voltage increasing, an erased data state and a programmed data state [para. 72 as well as para. 122], and the method further includes the steps of:
maintaining voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings as the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [see Fig. 18, the bit lines for programming are applied with 0V, para. 71, thus when a memory cell is programmed in first period, the bit line coupled to that memory cell remains at 0V during the second period and the third period of the initial program stage];
ramping voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings to the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the steady state voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71, thus, when a memory cell is programmed during the first period, and after that is set for erasing, the bit line coupled to that memory cell is applied with 0V during the first period and applied with VDD during the second period and the third period of the initial program stage];
ramping voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings to the steady state voltage to enable the programming of the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings during the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the programmed data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period and the second period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71. In a first step 1801a, all the cell strings of all the page groups in block 1606 are loaded with ‘inhibit’ data. To do so, all the bit lines BL[0:k] are supplied with VDD (data 1), para. 119; thus, when a memory cell is programmed during the third period, the bit line coupled to that memory cell is applied with VDD during the first period and second period, after that it is applied with 0V during the third period]; and
maintaining voltage applied to ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings as the inhibiting voltage to inhibit the programming of the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings during the second period and the third period of the initial program stage in response to the ones of the plurality of bit lines coupled to the memory cells targeted for the erased data state of the at least one subsequent one of the plurality of strings being biased to the inhibit voltage during the first period of the initial program stage [the bit lines for programming and inhibit are applied with 0V and VDD, respectively, para. 71; thus, when a memory cell is set for erasing, the bit line coupled to that memory cell remains at VDD for inhibiting].
Regarding claim 18, Hsu in combination with Dunga et al. teach the limitations with respect to claim 16.
Furthermore, Hsu discloses a duration of the first period of the initial program stage is adjustable, the first period of the initial program stage being shorter than the at least one subsequent program stage [see Examiner Markup Hsu’s Figure 18, during an MPS operation, loading multiple page buffers' data to multiple blocks generally takes 1 or less than 1 μs. Compared with 30 μs program pulse, loading time from page buffer to blocks is small, para. 77].
Regarding claim 19, Hsu in combination with Dunga et al. teach the limitations with respect to claim 16.
Furthermore, Hsu discloses further including the step of ramping voltage applied to ones of the plurality of bit lines coupled to the memory cells of the at least one subsequent one of the plurality of strings from one of the steady state voltage and the inhibiting voltage to another of the steady state voltage and the inhibiting voltage before ramping voltage applied to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings to the gate transistor voltage during the initial program stage [see Fig. 18, in a first step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1) from 0V, para. 119].
Regarding claim 20, Hsu in combination with Dunga et al. teach the limitations with respect to claim 16.
Furthermore, Hsu discloses wherein the boost stage includes, in sequence, a first ending period and a second ending period and a third ending period, and the control means is further configured to apply the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings during the boost stage to leak a boost potential of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings, the gate transistor voltage to the drain-side select gate transistor of each of the memory holes including the memory cells of the at least one subsequent one of the plurality of strings ramped back down to the steady state voltage during the first ending period of the boost stage [see Fig. 18, in a first step 1801a, all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, as shown in 1802a through 1802b, para. 119].
Response to Arguments
Applicant's arguments filed with respect to independent claims 1, 8 and 14 have been fully considered but they are not persuasive.
With respect to independent claims 1, 8 and 14, Applicant asserted that Hsu (paragraphs [0117]-[0126] of Hsu) and Dunga (paragraphs [0089]-[0098] of Dunga) either do not show or suggest programming two or more strings in immediate sequence under a common pulse/voltage setup or sequential programming of multiple strings during the same program pulse without re-initialization of control voltages, see Applicant’s Remarks page 21. This particular remark is not considered persuasive.
Hsu discloses preform operations of repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation [para. 9]. Moreover, Hsu also shows in Figure 18 Vpgm applied to word line remains unchanged while programming two strings.
For the above reason, the previously applied rejection is considered proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825