Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chu (U.S. Patent Application 2022/0415418).
Claim 1. A method, comprising: generating level indicator data based on first data (control logic 512, Chu Fig 5A, generating level indicator data through 510 based on first data for 301, first data taught in Fig 11 ), wherein the first data is to be stored in a memory device (301, storing taught in Fig 12A) based on a first programming operation and a second programming operation (1st and 2nd program taught in Fig. 10); performing a programming operation (Vpgm) to store the level indicator data in a first cell of a memory cell array of the memory device (a first memory cell in array 301 Fig 5A); and performing the first programming operation (Vpgm) to store the first data in a second cell of the memory cell array of the memory device (second memory cell in array 301, Chu Fig 5A).
Claim 2. The method according to claim 1, wherein the method further comprises: storing the level indicator data in one or more internal latches of a page buffer of the memory device (latches of page buffer 504 Fig 5A) before performing the programming operation (Fine programming after storing taught in Fig 12A) to store the level indicator data in the first cell (the first memory cell in array 301 Fig 5A).
Claim 3. The method according to claim 2, wherein the method further comprises: storing the first data in the one or more internal latches of the page buffer (504 Fig 5A) of the memory device before performing the programming operation to store the level indicator data in the first cell and before performing the first programming operation (Coarse programming after storing taught in Fig 12A) to store the first data in the second cell (the second memory cell in array 301 Fig 5A).
Claim 4. The method according to claim 1, wherein generating the level indicator data based on the first data (control logic 512, Chu Fig 5A, generating level indicator data through 510 based on first data for 301) comprises generating the level indicator data based on parity information of the first data (the level indicator data based on parity information taught in Fig 11).
Claim 5. The method according to claim 1, wherein performing the programming operation (Vpgm) comprises performing the programming operation to store the level indicator data in a single-level cell (SLC) mode (SLC taught in Chu [0039]).
Claim 6. The method according to claim 1, wherein after performing the first programming operation (Vpgm through control logic 512), the method further comprises: reading the level indicator data from the memory cell array (in memory cell array 301); retrieving the first data by reading the first data from the memory cell array (controller 512 allows for reading first data in memory cell array 301); generating second data based on the level indicator data and the retrieved first data (second data taught in Fig 11); and performing the second programming operation to store the second data in the memory cell array of the memory device (second programming operation taught in Fig 6 to store in memory cells of array 301 Fig 5A, second data taught in Fig 11).
Claim 7. The method according to claim 6, wherein retrieving the first data by reading the first data from the memory cell array comprises: performing a first read operation of the second cell using a first set of read voltages to generate third data (Verify comprising a first read taught in Fig 11 to generate a verify result, data taught in Fig 11); and performing a second read operation of the second cell using a second set of read voltages to generate fourth data (Second verify comprising a second read taught in Fig 10 using a second set of read voltages to generate another verify result, data taught in Fig 11); and wherein generating the second data based on the level indicator data (based on level indicated in Fig 10) and the retrieved first data comprises generating the second data based on the level indicator data, the third data, and the fourth data (data for each taught in Fig 11).
Claim 8. The method according to claim 1, wherein the first cell and the second cell are coupled to a same bit line of the memory cell array (1st and 2nd cells coupled to same bit line in array, Chu Fig 3).
Claim 9. The method according to claim 1, wherein the level indicator data and the first data (data taught in Fig 11) are programmed into different pages of a same block of the memory cell array (different pages of page buffer 504, pages P1-P4 taught in Fig 7BV).
Claim 10. The method according to claim 1, wherein the level indicator data and the first data (data taught in Fig 11) are programmed into different blocks of a same plane of the memory cell array (different blocks 702 taught in Fig 7B).
Claim 11. A memory device, comprising: a memory cell array (301, Chu Fig 5A); and a peripheral circuit coupled to the memory cell array (control logic 512, Chu Fig 5A) and configured to (configured to is functional language) perform operations comprising: generating level indicator data based on first data (control logic 512, Chu Fig 5A, generating level indicator data through 510 based on first data for 301, first data taught in Fig 11 ), wherein the first data is to be stored in the memory device (301, storing taught in Fig 12A) based on a first programming operation and a second programming operation (1st and 2nd program taught in Fig. 10); performing a programming operation (Vpgm) to store the level indicator data in a first cell of the memory cell array of the memory device (a first memory cell in array 301 Fig 5A); and performing the first programming operation (Vpgm) to store the first data in a second cell of the memory cell array of the memory device (second memory cell in array 301, Chu Fig 5A).
Claim 12. The memory device according to claim 11, wherein the operations further comprise: storing the level indicator data in one or more internal latches of a page buffer of the memory device (latches of page buffer 504 Fig 5A) before performing the programming operation (Fine programming after storing taught in Fig 12A) to store the level indicator data (the first memory cell in array 301 Fig 5A).
Claim 13. The memory device according to claim 12, wherein the operations further comprise: storing the first data in the one or more internal latches of the page buffer (504 Fig 5A) of the memory device before performing the programming operation (Coarse programming after storing taught in Fig 12A) to store the level indicator data in the first cell and before performing the first programming operation to store the first data in the second cell (the second memory cell in array 301 Fig 5A).
Claim 14. The memory device according to claim 11, wherein generating the level indicator data based on the first data (control logic 512, Chu Fig 5A, generating level indicator data through 510 based on first data for 301) comprises generating the level indicator data based on parity information of the first data (the level indicator data based on parity information taught in Fig 11).
Claim 15. The memory device according to claim 11, wherein the first cell and the second cell are coupled to a same bit line of the memory cell array (1st and 2nd cells coupled to same bit line in array, Chu Fig 3).
Claim 16. The memory device according to claim 11, wherein the level indicator data and the first data (data taught in Fig 11) are programmed into different pages of a same block of the memory cell array (different pages of page buffer 504, pages P1-P4 taught in Fig 7BV).
Claim 17. The memory device according to claim 11, wherein the level indicator data and the first data (data taught in Fig 11) are programmed into different blocks of a same plane of the memory cell array (different blocks 702 taught in Fig 7B).
Claim 18. A memory system, comprising: a memory device, comprising: a memory cell array (301, Chu Fig 5A); and a peripheral circuit coupled to the memory cell array (control logic 512, Chu Fig 5A) and configured to (configured to is functional language) perform operations comprising: generating level indicator data based on first data (control logic 512, Chu Fig 5A, generating level indicator data through 510 based on first data for 301, first data taught in Fig 11 ), wherein the first data is to be stored in the memory device (301, storing taught in Fig 12A) based on a first programming operation and a second programming operation (1st and 2nd program taught in Fig. 10); performing a programming operation (Vpgm) to store the level indicator data in a first cell of the memory cell array of the memory device (a first memory cell in array 301 Fig 5A); and performing the first programming operation (Vpgm) to store the first data in a second cell of the memory cell array of the memory device (second memory cell in array 301, Chu Fig 5A); and a controller (comprising control logic 512, Chu Fig 5A) coupled to the memory device (comprising memory 301) and configured to (configured to is functional language) send one or more signals to the memory device to initiate the operations (configured send one or more signals through voltage generator 510 to the memory device 301 Fig 5A to initiate the operations).
Claim 19. The memory system according to claim 18, wherein the controller is configured to (configured to is functional language) perform one or more operations comprising: sending a first signal to the memory device (301 Fig 5A) to initiate the programming operation (Vpgm 1 Fig 10) to store the level indicator data and to initiate the first programming operation (Vpgm 1 Fig 10) to store the first data (data taught in Fig 11); sending a second signal to the memory device to initiate a read operation (verify taught in Fig 10) to read second data from the memory device (second data from device 301 Fig 5A, data taught in Fig 11), wherein the second data is generated by the memory device using the level indicator data and the first data (of Vpgm 1); and sending a third signal to the memory device to initiate the second programming operation to store the second data (Vpgm 2 Fig 10, data taught in Fig 11 ).
Claim 20. The memory system according to claim 19, wherein the controller further comprises a decoder and an encoder (Decoder 508 Fig 5A decodes row signals and combined with voltage gen 510 encodes signal into 301), and the one or more operations further comprise: receiving the second data from the memory device (second data taught in Fig 11) after sending the second signal (Verify after Vpgm 1) to the memory device to initiate the read operation to read the second data (read of verify operation taught in Fig 10); decoding the second data using the decoder (decoder 508); and encoding the decoded second data into fifth data using the encoder (through controller 512 and voltage generator 510, Fig 5A), wherein sending the third signal to the memory device to initiate the second programming operation (Vpgm 2 Fig 10) to store the second data comprises sending the third signal to the memory device (sending a third signal to 301 Fig FA) to initiate a program operation to store the fifth data in the memory device (fifth data taught in Fig 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827