Prosecution Insights
Last updated: July 17, 2026
Application No. 18/639,973

MEMORY DEVICE

Non-Final OA §102§103
Filed
Apr 19, 2024
Priority
Feb 07, 2024 — TW 113105146
Examiner
ZHU, SHENG-BAI
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
6m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
444 granted / 714 resolved
-5.8% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
64 currently pending
Career history
780
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
95.1%
+55.1% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 714 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Specification Objection The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections – 35 U.S.C. 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1-4, 6, 7, 9 and 10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsunekawa (U.S. Patent Pub. No. 2022/0415912). Regarding Claim 1 FIG. 2 of Tsunekawa discloses a memory device comprising a plurality of memory cells, wherein each of the memory cells comprises: a bottom electrode (1) disposed on a substrate (6); a ferroelectric layer (2) disposed on the bottom electrode; a barrier layer (3) disposed on the ferroelectric layer; and a top electrode (4) disposed on the barrier layer, wherein the barrier layer is interposed between the top electrode and the ferroelectric layer, and a thickness (1nm-4nm) of the barrier layer [0033] is less than a thickness (5nm-20nm) of the ferroelectric layer [0032]. Regarding Claim 2 Tsunekawa discloses the barrier layer comprises magnesium oxide (MgO) [0026]. Regarding Claim 3 Tsunekawa discloses the ferroelectric layer comprises hafnium zirconium oxide (HfZrO, HZO) [0002]. Regarding Claim 4 Tsunekawa discloses a material of the bottom electrode is different from a material of the top electrode [0027]. Regarding Claim 6 Tsunekawa discloses the thickness of the ferroelectric layer is about 6 nm [0032]. Regarding Claim 7 Tsunekawa discloses the thickness of the barrier layer is less than or equal to about 1 nm [0033]. Regarding Claim 9 FIG. 4 of Tsunekawa discloses a gate structure disposed on the substrate; and a drain and a source respectively disposed in the substrate at opposite sides of the gate structure, wherein the drain is electrically connected to the bottom electrode, and the source is electrically connected to a bit line (BL). Regarding Claim 10 FIG. 2 of Tsunekawa discloses the bottom electrode (1) directly contacts the ferroelectric layer (2), and the barrier layer (3) directly contacts the top electrode (4) and the ferroelectric layer. Claim Rejections – 35 U.S.C. 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Tsunekawa, in view of Kim (KR 20250120639, machine-translation provided). Regarding Claim 5 Tsunekawa discloses Claim 4, wherein the bottom electrode comprises titanium nitride (TiN) [0031]. Tsunekawa is silent with respect to “the top electrode comprises tungsten (W)”. FIG. 2 of Kim discloses a similar memory device, wherein the bottom electrode comprises titanium nitride (TiN) and the top electrode comprises tungsten (W). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tsunekawa, as taught by Kim, because such material) substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06. The ordinary artisan would have been motivated to modify Tsunekawa in the above manner for purpose of improving TER effect (text of Kim). Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Tsunekawa, in view of Pesic (U.S. Patent Pub. No. 2023/0054171). Regarding Claim 8 Tsunekawa discloses Claim 6. Tsunekawa is silent with respect to “the thickness of the barrier layer is less than or equal to about 0.5 nm”. FIG. 2 of Kim discloses a similar memory device, wherein the thickness of the barrier layer is less than or equal to about 0.5 nm [005]. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tsunekawa, as taught by Kim, because such material) substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06. The ordinary artisan would have been motivated to modify Tsunekawa in the above manner for purpose of improving TER effect (text of Kim). Furthermore, said thickness is related to the device size and the barrier property of the material. Therefore, said thickness is considered to be a result effective variable. The claim to a specific thickness therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Pertinent Art US 20210398990 discloses a gate structure disposed on the substrate; and a drain and a source respectively disposed in the substrate at opposite sides of the gate structure, wherein the drain is electrically connected to the bottom electrode, and the source is electrically connected to a bit line. US 20230054171 discloses a memory device, comprising: a bottom electrode; a ferroelectric layer disposed on the bottom electrode; a barrier layer disposed on the ferroelectric layer; and a top electrode disposed on the barrier layer, wherein the barrier layer is interposed between the top electrode and the ferroelectric layer, and a thickness of the barrier layer is less than a thickness of the ferroelectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Apr 19, 2024
Application Filed
Jun 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
68%
With Interview (+6.0%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 714 resolved cases by this examiner. Grant probability derived from career allowance rate.

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