DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yasar et al (US 2003/0034244 A1).
As to claim 1, Yasar discloses a substrate processing method, comprising:
placing a substrate 21 in a substrate processing apparatus 20 (Fig. 3, [0032]);
applying source power 27 (“RF generator”) to the substrate processing apparatus [0032]; and
applying bias power 28 (“RF bias generator”) to the substrate processing apparatus [0032],
wherein applying the source power to the substrate processing apparatus includes:
providing the substrate processing apparatus with a first radio-frequency (RF) power with a first pulse having a first period (as depicted in Fig. 4, “ICP Power”); and
providing the substrate processing apparatus with a second RF power with a second pulse having a second period (as depicted in Fig. 4, “RF Wafer Bias Power”).
Yasar fails to explicitly disclose that the first period is longer than the second period. However, Yasar teaches that the relative portions of deposition and etch modes, and their respective process parameters, may be varied during the cycle or from cycle to cycle to affect the best overall final result [0042]. A typical process parameter is time. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide for the cited time periods in the method of Yasar in order to affect the best overall result by providing a desired amount of deposition and a desired amount of etching based on the time that the deposition and etching species are present.
As to claims 2 and 3, Yasar fails to explicitly disclose that the first RF power is greater or less than the second RF power. However, RF power is also a typical process parameter. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide for the RF powers in the method of Yasar in order to affect the best overall result by providing a desired amount of deposition and a desired amount of etching based on the desired reactivity and directionality desired for the reactive species.
As to claim 4, Yasar discloses that applying the bias power to the substrate processing apparatus includes providing the substrate processing apparatus with the bias power with a third pulse having a third period, (see Figure 5, “RF Substrate Bias Power” as shown by the dashed line is lower during deposition and higher during etching, thus providing a second and third pulse periods. Figure 5 also depicts that the third period is the same as the second period (generally equal times as shown along the “Process Time” x-axis).
As to claim 5, Yasar discloses that a portion of applying the bias power is performed simultaneously with applying the second RF power (as shown in the “Deposition” part of the cycle, both ICP Power and RF Substrate bias power are applied).
As to claim 6, Yasar discloses that the bias power is a non-sinusoidal wave (see Figure 5).
As to claim 7, Yasar discloses that applying the bias power and the applying the first RF power overlap or do not overlap each other in terms of time (see Figure 4, where the first RF power during deposition does not overlap with the wafer bias power during etching).
As to claim 8, Yasar discloses that applying the first RF power continues for a first time duration (as depicted in Figure 5, about 25 seconds, “ICP Power” short-dashed line),
applying the second RF power continues for a second time duration (about 10 seconds, the “RF Substrate Bias Power” line),
the first time duration is the same as the first period (as defined by the claim), and
the second time duration is longer than the second period as defined by the claim).
As to claim 9, Yasar discloses that each of the first time duration and the second time duration is greater than about 100 milliseconds, and the second period is equal to or less than about 100 milliseconds (Yasar has times periods of seconds, which is greater than milliseconds).
As to claim 10, Yasar discloses that applying the first RF power and applying the second RF power are alternately and repeatedly performed (see Figure 4, [0040]).
As to claim 11, Yasar discloses applying a smaller level of source power to the substrate processing apparatus, rather than no source power [0041]. However, this is for convenience of switching from deposition to etching quickly [0041]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide no power as cited in the method of Yasar because the process can be optimized to provide for no deposition during the etching cycle to achieve desired final results of deposition.
As to claim 12, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply no source power to the substrate processing apparatus after stopping the second RF power stops and before applying the first RF power begins again in the method of Yasar in order to optimize the process for best results of the presence of deposition and etching species to achieve desired results of deposition.
As to claim 13, see the rejection of claim 1. Yasar discloses that the first RF power is applying during the deposition process, and the second RF power and bias power is applied during the etching process as cited (Fig. 4, Fig. 5).
As to claim 14, Yasar discloses performing the deposition process on the substrate and performing the etching process on the substrate alternately and repeatedly ([0040], Fig. 4-Fig. 5).
As to claim 15, Yasar discloses that after stopping the etching process before beginning the deposition process, that the power levels decrease rather than stopping. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply no power as cited in the method of Yasar in order to optimize the process for best results of the presence of deposition and etching species to achieve desired results of deposition.
As to claim 16, Yasar discloses that the process parameters may be changed for best results [0042]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have the second period be shorter than the first period in the method of Yasar in order to optimize the process for best results of the duration of deposition and etching species to achieve desired results of deposition.
As to claim 17, Yasar discloses that the substrate processing apparatus includes:
a process chamber that includes a process space (Fig. 1);
a chuck 22 [0032] in the process chamber; an upper electrode 26 overlapping and spaced apart from the chuck (see Fig. 3); and
a lower electrode 22 in the chuck (to which the wafer RF bias is applied, [0032]),
wherein the chuck includes:
a chuck body that supports the substrate (see Fig. 3); and
a chuck electrode in the chuck body (to which the wafer RF bias is applied, [0032]).
Further, apparatus limitations are given little patentable weight in method claims. Apparatus limitations, unless they affect the process in a manipulative sense, may have little weight in process claims. In re Tarczy-Hornoch 158 USPQ 141, 150 (CCPA 1968); In re Edwards 128 USPQ 387 (CCPA 1961); Stalego v. Heymes 120 USPQ 473, 478 (CCPA 1959); Ex parte Hart 117 USPQ 193 (PO BdPatApp 1957); In re Freeman 44 USPQ 116 (CCPA 1940); In re Sweeney 72 USPQ 501 CCPA 1947).
As to claim 18, Yasar discloses that the first RF power is applied to the upper electrode, and the bias power is applied to the lower electrode (see Fig. 3). Yasar fails to discloses that the second RF power is applied to the upper electrode. However, Yasar discloses in an alternative embodiment that the second RF power for etching may be applied to an antenna (Fig. 3a), which encompasses providing the second RF power to a different electrode in the chamber. It is also well known to form plasmas by etching by applied RF power to the upper electrode. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply the first and second RF powers to the upper electrode as cited in the method of Yasar because Yasar recognizes that other forms of plasmas may be used for the process steps, and etching and deposition by providing RF power to an upper electrode is a useful, functionally equivalent technique for forming plasma species for both etching and deposition.
As to claim 19, Yasar fails to disclose that each of the first RF power, the second RF power, and the bias power is applied to the lower electrode. However, like the different embodiment of Figure 3a, other configurations for forming plasma are useful such as applying the powers to a lower electrode as cited. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply the first RF, second RF and bias powers as cited in the method of Yasar because such is a functionally equivalent technique for forming plasma species for both etching and deposition.
As to claim 20, Yasar discloses
performing the deposition process on the substrate continues for a first time duration (as shows in Figure 5),
performing the etching process on the substrate continues for a second time duration (as shows in Figure 5), and
the first period is the same as the first time duration (as defined by the claim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Martinez et al (US 12,592,361 B2), Sridhar et al (US 2025/0273439 A1) and Chen et al (US 2023/0377895 A1) are cited to show general techniques of varying RF power and bias power. Martinez et al (US 2024/0055228 A1) is cited to show varying pulse amplitudes and width, i.e., time [0053]. Tanaka (US 5,976,327) is cited to show reasons for varying various parameters of a deposition or etching process (col. 6, lines 37-62).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANITA K ALANKO whose telephone number is (571)270-0297. The examiner can normally be reached Monday-Friday, 9 am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANITA K ALANKO/Primary Examiner, Art Unit 1713
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